A method of packaging a semiconductor device (10) partitions a distribution substrate (20, 40) into regions (31-34) such that attachment points (22) for electrically coupling to the semiconductor device lie in a first region (31). A first set of conductors are routed from a portion of the attachment points to terminals in a second region (32). Another portion of the attachment points are assigned to available routing channels of the second region for disposing a second set of conductors across t...

The output signal of a CMOS power-on reset circuit changes state upon detecting a predetermined threshold of the power supply voltage during the start-up transient. During the power-up of the power supply voltage, the output signal of the power-on reset circuit ramps up with the power supply voltage until the latter reaches a first predetermined level whereat a control signal begins to track the increasing power supply voltage, less two diodes potentials. Upon reaching the turn-on potential of a...

An optical sensor package that includes an optical sensor die is mounted by flip chip interconnect onto a lead frame in a "die-down" orientation, that is, with the active side of the optical sensor die facing the lead frame. An opening is provided in the lead frame die paddle (pad), and light passes from outside the package through the opening in the lead frame die pad onto light collection elements on the active side of the chip.

A semiconductor package includes a leadframe, an elevated die paddle disposed above the leadframe, a first die attached to a lower surface of the elevated die paddle to support the first die within the semiconductor package, and a second die attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having a lower lead and an elevated die paddle structure, attaching a first die to the elevated die paddle structure with a die adhesive (DA) for supp...

A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A...

A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41) of the device. The one or more localized regions of doping (61,62,63) are spaced apart from the body regions (44,46) to avoid detrimentally impacting device breakdown voltage. In an alternative embodiment, a groo...

A semiconductor device (10) uses a plurality of floating field conductors (26, 28) to provide a substantially uniform electric field along the surface of the drift region (17) of the device (10). This substantially uniform electric field increases the breakdown voltage per unit length of the drift region (17).

A method of manufacturing a semiconductor component includes applying an encapsulant (211) to a wafer (210, 430), degassing the encapsulant (211), and separating the wafer (210, 430) into a plurality of semiconductor components. Manufactured in this manner, the encapsulant (211) of the semiconductor component is substantially devoid of air bubbles and voids.

An electronic component includes a substrate (301, 801), a leadframe (101, 601, 710) coupled to a first surface of the substrate (301, 801) and extending beyond the first surface and towards a second surface of the substrate (301, 801), and an electrically conductive layer coupled to the second surface and coplanar with a contact portion of the leadframe (101, 601, 710) where the leadframe (101, 601, 710) and the electrically conductive layer form a package around the substrate (301, 801).

A temperature detection circuit that minimizes the influence of variations due to manufacturing process and other factors, and can be used at high temperatures near its maximum usable temperature. According to the present invention, a temperature detection circuit is provided which comprises: a first current source coupled to a detection node; a second current source coupled in series to the first current source, and coupled to the detection node, the second current source having a temperature c...