A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead fram...

A N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal SiO.sub.2 which is about half as t...

A system (10) for processing wafers and cleaning wafer cassettes (160, 260, 460) includes a work cell (12) having a plurality of processing stations (14) for processing wafers, and at least one processing/cleaning station (30, 130, 230, 430) for receiving and delivering wafers to and from a wafer cassette (160, 260, 460), a transfer mechanism (16) for moving the wafers between the plurality of processing stations (14) and the cleaning station (30). The cleaning station (30, 130, 230, 430) may ha...

A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer (8). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change .DELTA.Rs=Rsi-...

A system (30) and method for preheating molding compound in the form of resin pellets (20) used in molding integrated circuits (50). A slanted plate (36) is connected to an electrode (31) to preheat resin pellets (20). The slanted plate (36) produces a temperature gradient in pellets (20) with a high temperature end (21) and a lower temperature end (22). A preheated pellet (20) with the lower temperature end (22) first is placed in a mold pot (40). A transfer ram (46) contacts the high temperatu...

A process is disclosed for inhibiting undesired diffusion of implanted dopants during and after dopant activation, as can occur during source/drain anneal. Undesired dopant diffusion is minimized by a dopant blocking layer, which is applied to the semiconductor body prior to dopant activation, and preferably prior to dopant implantation. The composition of the blocking layer is selected in accordance with the diffusion mechanism of the dopant to be implanted so that the concentration of lattice ...

A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During wafer polishing particles build up on the polishing pad (114) reducing its effectiveness. Either during or in between wafer polishing (or both), conditioning head (122) is applied to pad (114) to remove the particles from pad (114) into the slurr...

The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the ...

An improved power-up circuit utilizing a simple current channel to rapidly charge or discharge nodes during the power-up transient, the time from when the circuit is signaled to power up to the time when the circuit becomes fully functional. The invention allows critical nodes previously limiting the power-up sequence to be rapidly charged to significantly improve the power-up performance of power savings circuits.

An ESD protection structure which includes, preferably a single semiconductor chip, a forward SCR for coupling across a source of potential and a reverse SCR for coupling across the same source of potential which is non-symmetrical to the forward SCR. The breakdown voltage of the forward SCR is different from the breakdown voltage of the reverse SCR. Each of the SCRs has a separate triggering mechanism. None of the anode, cathode and triggering elements of the forward SCR are common to the rever...