A DC-DC power converter cell is disclosed which incorporates novel control circuits that operates the cell at efficiencies of 88%. This cell also has control-in and control-out terminals whereby multiple cells are intercoupled to operate in synchronization with each other as a versatile system of cells. Manufacturing cost is reduced by utilizing a simply configured single-turn high-frequency transformer in each cell, and by operating at efficiencies that reduce cooling requirements.

In a video-on-demand system, disc-based video streams are seamlessly replaced with memory-based video streams. This is achieved by first switching each disc-based video stream to a mixed video stream; and later, switching each mixed video stream to a memory-based video stream.

A module for preventing instability in systems which test integrated circuit chips resides between the tester unit and the chip that is being tested. This module is characterized as including a plurality of phase-shifting circuits which couple respective output signals from output transistors on the chip onto signal lines to the tester unit. Each phase-shifting circuit includes an inductor which counteracts and cancels any capacitive phase shift that is produced by the input impedance of the cor...

A high density integrated circuit module is comprised of a plurality of integrated circuit chips; each of the chips has top and bottom surfaces and thin sides; and all of the chips are arranged in a stack in which the sides of the chips form multiple faces of the stack. Also, in accordance with the invention, a selected face of the stack has a zigzag shape which exposes a portion of the top surface of each chip on that face; and, bonding pads for carrying input/output signals to/from the chips a...

A layered electronic assembly contains a plurality of integrated circuit chips that are arranged in a stack; respective adhesive layers interleave the chips and hold them together; and I/O leads on the chips extend to one face of the stack. Also, the chips in the stack have respective thicknesses which vary from chip to chip; the I/O leads are offset from one edge of the chip on which they lie by respective distances which vary from chip to chip; the adhesive layers in the stack have respective ...

An electronic system for processing sampled data input signals includes an electronic memory which stores a set of preprocessed vectors V.sub.1 f(m, . . . ) thru V.sub.N *f(m, . . . ) where f(m, . . . ) is a sampled data function, having any number of dimensions m, . . . . * is a convolution operator, and V.sub.1 thru V.sub.N are a finite set of N unprocessed vectors each of which represents an anticipated group of input signal samples. After these preprocessed vectors are stored, input signals ...

A given target temperature profile T is produced in a workpiece as it passes through an elongated passageway of a belt furance by the steps of: (1) determining a set of temperature setting TS.sub.X for the belt furnace thermostats which satisfy an equation f(.alpha.,TS.sub.X,CF.sub.Y).apprxeq.T where .alpha. is a set of thermal parameters for the workpiece, CF.sub.Y is a set of correction factors, and f( ) is a function which approximates the temperature of said workpiece based on TS.sub.X,.alph...

Interconnect circuitry is formed on a selected face of several separate layered electronic assemblies simultaneously. This circuitry interconnects the I/O leads on each assembly, and it is formed by the steps of: (a) placing a plurality of the assemblies in a fixture with spacers between each assembly; (b) aligning to a single plane, one face of each assembly in the fixture on which the circuitry is to be formed; (c) mechanically squeezing the assemblies and spacers together with the fixture suc...

A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in the chip which contains all the transistors and their interconnections within the cell; at least one of the sidewalls is shaped to include a step which gives the cell a narrow top and a wide bottom; and one or more of the cell's transistors lie...

A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel field-effect transistors having set a reset nodes. Also in each cell, a first P-channel transistor couples a first select line to the set node; a first bipolar transistor couples the set node to a first bit line; a second P-channel trnasistor couples a second select line to the reset node; and a second bipolar transistor couples the reset node to a second bit line. Data is read from one port of the...