An MOS device is provided having a channel-stop implant placed between active regions and beneath field oxides. The channel-stop dopant material is a p-type material of atomic weight greater than boron, and preferably utilizes solely indium ions. The indium ions, once implanted, have a greater tendency to remain in their position than boron ions. Subsequent temperature cycles caused by, for example, field oxide growth do not significantly change the initial implant position. Thus, NMOS devices u...

A computer system includes a real-time interrupt that causes the operating system to determine which isochronous tasks are pending. In one embodiment, applications that include isochronous tasks are certified to be well-behaved and the operating system will only initiate applications that are known to be well-behaved by checking a list of certified applications. The operating system will not initiate an application if insufficient resources are available for executing the tasks of the applicatio...

A method of managing context-sensitive help data for a computer system includes displaying a plurality of program components to a user for interaction, and retrieving from a first memory area having a first access time first help data corresponding to a first of the components, where the first component is not interacted with by the user. Then store the first help data in a second memory area having a second access time less than the first access time. Subsequent to storing the first help data, ...

A routing scheme using intention packets is contemplated. At times, one or more switching devices within a network may become overloaded with traffic or may encounter other adverse transmission conditions. When this occurs, a switching device may drop one or more packets to alleviate some of the congestion or other adverse condition. The switching devices may support a particular amount of resources (e.g. bandwidth, buffers, etc.) in and out of each of their ports. When a packet or a header port...

A method and apparatus for driving a plurality of addressable elements consist of driving and selectively enabling one or more addressable elements arranged as an M.times.N array using two drivers. The columns may be addressed in parallel. Columns may be coupled to a conductor by a charge transfer/isolation circuit. A voltage waveform or pulse train may be propagated down the display conductor such that a pulse is present on the display conductor for each element of a row of elements to be addre...

A system for scheduling storage accesses of multiple continuous media streams may include a plurality of media stream clients. Associated with each media stream client is one of a plurality of media stream managers. Each media stream manager maintains a ring of buffers configured to buffer media stream data between its associated media stream client and one or more storage systems. A different deadline queue may be associated with each one of the storage systems. Each deadline queue may be confi...

In a processor a reorder buffer maintains a load/store (LS) fault address register (LSFAR). When the processor's load/store unit reports most LS exceptions, the reorder buffer redirects the microcode unit of the processor to execute a fault handler indicated by an address stored in the LSFAR. The LSFAR may be mapped into the register space of the processor. It may be written by a microcode routine with the address of a specific fault handler at the beginning of a microcode routine or at any time...

Random access memory (RAM) may be provided in a processor for implementing microcode patches. The patch RAM may loaded by a microcode routine that is part of the normal microcode contained in a microcode read only memory (ROM) unit of the processor. When the processor powers-up, it uses its internal ROM microcode only if no patches are installed. If patches are installed and a microcode line is accessed for which a patch is enabled, the patch is executed instead of the microcode line. A patch ma...

An array of storage devices may be provided in which data is both striped and mirrored across the array. Data may be organized in stripes in which each stripe is divided into a plurality of stripe units. The stripe units may be mapped sequentially to consecutive storage devices in the array for each data stripe. Each data stripe is also mirrored within the array as a mirrored data stripe. Each mirrored data stripe is also divided into a plurality of stripe units. The stripe units of the mirrored...

A controller for a powered loudspeaker including a bus monitor configured to monitor a bus for activity and a click suppression unit coupled to the bus monitor and configured to control speaker volume by ramping the volume down if an absence of data on the bus is detected, and restoring the volume once bus activity begins again. In this manner, undesired clicks and hisses upon power up and power down are minimized.