A continuous speech recognition system having a speech processor and a word recognition computer subsystem, characterized by an element for developing a graph for confluent links between confluent nodes; an element for developing a graph of boundary links between adjacent words; an element for storing an inventory of confluent links and boundary links as a coding inventory; an element for converting an unknown utterance into an encoded sequence of confluent links and boundary links corresponding...

A telephone call responding system which allows the user to respond to an incoming telephone call without actually speaking to the caller personally, and, if desired, without having to pick up the telephone to answer a call. To activate the responder system, the user, upon receiving an incoming telephone call, selects one of a plurality of call response messages by actuating a control key of the responder system corresponding to the desired message. Once activated, the responder system connects ...

A pseudorandom number generator includes: an M-sequence generator having a plurality of stages a.sub.i ; and a matrix product circuit which combines a matrix G having components g.sub.ji with the stages a.sub.i to provide output elements b.sub.j of a number, each b.sub.j being represented by the expression,

The invention relates to a method for reducing a transient thermal mismatch between a first component and a second component which are in mechanical contact with one another. The temperature of the first component is controlled by the amount of energy dissipated thereby. The amount of energy dissipated is controlled as a function of a data pattern input into the first component which causes a certain number of gates within the component to switch per clock cycle. By determining the desired energ...

A method for testing protocol converters is presented, which permits the achievement of a test of all commands, independently of a corresponding test system. A modified protocol converter itself is used for the test. With the help of this method, a test for conversion of data structures can be carried out, of a slow protocol into the corresponding data structures of a fast protocol in the original speed.

An apparatus and a method for performing subroutine call and return operations in a computer having a processor with an instruction prefetch mechanism which includes a branch history table for storing target addresses of a plurality of branch instructions found in an instruction stream. The branch history table 22 contains a potential call instruction tag 37 and a return instruction tag 39. For each potential subroutine call instruction found in a prefetch instruction stream an address pair cont...

Described is a floating point processor comprising a multiply section and an add section, for performing a multiplication-add operation comprised of a multiplication operation prior to an addition operation which is using the result of the multiplication operation. The floating point processor comprises a multiply add controller (MAC1) which receives signals representing the exponents of the operands for the multiplication-add operation and signals representing the leading zero digits of an un-n...

A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Sai...

The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers. Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order stat...

A method for verification of configuration data which is expressive of the configuration of a computer system. A computer system having configuration data stored therein, further includes an identifier for uniquely identifying the computer system. A copy of the stored configuration data is encoded via an encoding method which uses the identifier, and the encoded configuration data is encrypted via an encryption method which uses a private key. Subsequently, the encrypted configuration data is de...