An apparatus and method for generating microscopic scan data of C-V and/or dC/dV over a scan area. A scanning microscope, for example a scanning force microscope, is provided with a voltage biased tip, for example, of tungsten, which is scanned across an area to derive the data. The data can be used to derive a plot of semiconductor dopant level across the scan area. Other material properties can be derived, for example, carrier generation and recombination rates and subsurface defects.

A self-adjusting impedance matching driver for a digital circuit. The driver has both a pull-up gate to VDD and a pull-down gate to ground. An array of gates is provided in parallel with each of the pull-up gate and the pull-down gate, with any one or more of such gates being selectively enabled in response to circuit means that monitors the impedance match between the output of the driver and the network it drives. By enabling selectively such gates, any impedance mismatch can be minimized. The...

A built-in, i.e., on-chip, self-test system for a VLSI logic or memory module. A deterministic data pattern generator is provided on the VLSI chip, and operates to test a chip module and provide a fail/no-fail result, along with data identifying where the fail occurred. This location data is captured and made available for subsequent utilization. The built-in test circuitry is programmable, and is provided with a looping capability to provide enhanced burn-in testing, for example.

A standard cell macro embedding method that extends the capability of conventional circuit placement routines by enabling them to automatically and optimally embed macro blocks within standard cell blocks. The macro blocks can be selected portions of the standard cell logic that are extracted and optimized for the purpose of enhancing performance, low power, density or functionality. The present invention optimally places these macros using a two pass placement process in which, first, Anchor an...

A method and apparatus for designing very large scale integrated circuit devices, most particularly level sensitive scan design (LSSD) devices, by inclusion of a plurality of distributed delay lines originating at input terminals of the device, and controlling the inhibiting and enabling of driver circuits connected to the output terminals of the device, as required to regulate operation of device drivers during a plurality of testing operations.

A modular photonic waveguide distribution system is disclosed which enables multi-directional and simultaneous communication within a multitude of coherent data processing units. The basic structure of an optical distributor element or module 1 is described and it is shown how the extension to complex data distribution structures can be achieved by respective combinations of the modules. Modes of operation and data selection are demonstrated.

A system for optimizing a logic network including expressing the logic network as an original graph having vertices, edges which connect the vertices and which represent connections in the logic network, and inversion markings for representing inverters in the logic network; determining a fundamental cycle(s) in the original graph; sorting the determined fundamental cycle(s) according to its parity; forming a final graph by processing the fundamental cycle(s) so as to optimize inverter placement...

A programmable logic array (PLA) is provided with a decoder at the input. Each product term line of the PLA has an associated power switch that is controlled by an output of the decoder. Only a portion of the PLA that includes the product term lines activated for a particular operation is powered up for that operation, thus minimizing power consumption.

A terminator for a transmission line that consumes substantially zero power. According to a preferred embodiment, a four device latch is provided, coupled at one side of the latch to the transmission line by way of a resistance. The size of the devices on the side of the latch connected to the transmission line and the value of the resistance are selected such that the combined impedance of the resistance and the device impedance to ground is substantially the same as the characteristic impedanc...

A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite of increased wire due to differential logic, and potential increased complexity in design software, the invention is actually readily adaptable to existing masterslice design systems.