A method and system for translating abstract structural or behavioral circuit descriptions to physically implementable files, preferably suitable for use in a Field Programmable Gate Array (FPGA) or other programmable device. A selection of layouts are generated for a cell definition (a function), allowing optimization and acceleration of circuit placement and routing without compromising design hierarchy or altering design function. Layout transformation functions may be manually initiated or a...

A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a "critical" stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. I...

A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables permits the computation of vector rotation and large FFTs in an efficient-parallel fashion within a unitary field programmable gate array chip, without off-chip memory for storing constants.

A method by which a two-dimensional array of logic elements may be interconnected such that they may be modeled as a three-dimensional array, while minimizing routing crossings. The result is an arrangement that is highly efficient for implementation in a silicon die. The preferred model may be extended to a three-dimensional torus where opposing faces of the array are considered to be adjacent. Routing flexibility is increased by increasing local interconnect while minimizing interconnect cross...

A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks, interconnect, and routing wires may be accomplished with switch matrices and programmable interconnect points.

A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

A method for designing an integrated circuit comprises the step of selecting a system-level parameterized module that performs a specified type of function. The method also includes the steps of specifying values for parameters of the selected system-level module and generating a netlist file from the selected system-level module. In one embodiment, the system-level parameterized module is selected from a family of system-level parameterized modules that each perform a particular function within...

A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory. This local memory allows large amounts of data to pass from one FPGA configuration (memory plane) to another with no external memory access, thereby transferring data to/from the storage elements in the logic plane at very high speed. Typically, all the local memory can be simultaneously transferred to...

The invention provides a Field Programmable Gate Array (FPGA) that initiates its own reconfiguration by driving its own output terminal and its own connected PROGRAM input terminal, permitting reliable self-reconfiguration of the FPGA. The signal forwarded to the PROGRAM input terminal triggers a reconfiguration sequence that, in turn, causes the signal received from the output terminal to be ignored. Therefore, the method of the invention is reliably stable and does not undesirably repeat, osci...

A system and method for conducting a multi-person, interactive auction, in a variety of formats, without using a human auctioneer to conduct the auction. The system is preferably implemented in software. The system allows a group of bidders to interactively place bids over a computer or communications network. Those bids are recorded by the system and the bidders are updated with the current auction status information. When appropriate, the system closes the auction from further bidding and noti...