An apparatus, system and method of executing a monolithic application program successfully on a grid computing system are provided. Before the program is executed on the grid computing system, the program is executed on a computer on which the program has previously been successfully executed. During its execution, the program is monitored to collect its runtime information. The runtime information is provided to the grid computing system. With this information the grid computing system is able ...

A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes "n" test patterns. In addition, the page table memory is allocated using a "true" sharing mode or a "false" sharing mode. The false sharing mode provides flexibility of performin...

A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a "no operation" (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a known memory area. In one embodiment, the processor has at least two pipelines that need to be aligned so that certain instructions are scheduled for the first pipeline and other i...

Generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths, is disclosed. Further, a preferred embodiment of the present invention includes a novel techique to efficiently realign or shift arbitrary streams to an arbitrary offset, regardless whether the alignments or offsets are known at the compile time or not. This technique enables the application of advanced alignment optimizations to runtime ali...

An image that includes ray traced pixel data and rasterized pixel data is generated. A synergistic processing unit (SPU) uses a rendering algorithm to generate ray traced data for objects that require high-quality image rendering. The ray traced data is fragmented, whereby each fragment includes a ray traced pixel depth value and a ray traced pixel color value. A rasterizer compares ray traced pixel depth values to corresponding rasterized pixel depth values, and overwrites ray traced pixel data...

A processing unit includes a read-only encryption key. Software is loaded into a system memory area from a non-volatile storage device. Software code image that resides in the system storage area includes a prefix value and a suffix value. The prefix value is combined with the master key from the processing unit to create a random value that is the seed for a hashing algorithm. The hashing algorithm uses the seed value with a signature formed from the blocks of code to form a result. Finally, af...

Generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths, is disclosed. Further, a preferred embodiment of the present invention includes a novel technique to efficiently realign or shift arbitrary streams to an arbitrary offset, regardless whether the alignments or offsets are known at the compile time or not. This technique enables the application of advanced alignment optimizations to runtime al...

A method for optimized specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the "intensity instruction" retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the appl...

The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

A method for an asymmetric heterogeneous multi-threaded operating system is presented. A processing unit (PU) provides a trusted mode environment in which an operating system executes. A heterogeneous processor environment includes a synergistic processing unit (SPU) that does not provide trusted mode capabilities. The PU operating system uses two separate and distinct schedulers which are a PU scheduler and an SPU scheduler to schedule tasks on a PU and an SPU, respectively. In one embodiment, ...