A semiconductor interconnect connection mechanism for attaching individual surface mounted semiconductor objects to multichip products whereby at least a portion of the electrical pathway between different objects on the top surface of surface mounted devices is not located on the top surface.

A chemical etchant for the removal of titanium-tungsten containing structures from the semiconductors and a method for removing the titanium-tungsten. The etchant comprising a solution of hydrogen peroxide, a salt of EDTA, and an acid, the acid capable of preventing the deposition of tin oxide. The method of removal comprises first obtaining a wafer containing titanium-tungsten. Second, immersing the wafer having titanium-tungsten thereon for a predetermined period of time in an etchant bath com...

A method for maintaining critical dimension during the etching of dielectrics, having the following steps: depositing a layer of photoresist over a layer of dielectric; patterning the photoresist such that voids are formed in the photoresist, the voids having sidewalls and a bottom; depositing an overlayer in an etch chamber; transferring the patterning in the photoresist to the dielectric.

A method of processing greensheets, wherein the following steps are performed: a) providing a greensheet having a width, length, thickness, a first side and a second side; b) bonding to the first side of the greensheet at least one strip, wherein the strip lies in a first plane; c) bonding to the second side of the green sheet at least one strip, wherein the strip lies in a second plane; d) processing the greensheet; and e) removing the strips from the processed greensheet.

An apparatus for applying a stress voltage to a device under test includes a stress voltage source, a constant voltage circuit having an input connected to the stress voltage source and an output connected to a control circuit for removing stress when current exceeds a predetermined level which is connected to the device under test. The constant voltage circuit provides a constant stress voltage to the device under test. A monitoring circuit measures the stress voltage applied to the device unde...

A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

An aqueous etchant composition containing about 0.01 to about 15 percent by weight of sulfuric acid and about 0.01 to about 20 percent by weight of hydrogen peroxide or about 1 to 30 ppm of ozone, and about 0.01 to 100 ppm of hydrofluoric acid is effective in removing polymer and via residue from a substrate or conductive material, and especially from an integrated circuit chip having aluminum lines thereon.

Disclosed is to provide an array substrate for display, a method of manufacturing the array substrate for display and a display device using the array substrate for display. The present invention is an array substrate for display, which includes: a thin film transistor array formed on an insulating substrate 1; a plurality of wirings 23 and 24 arranged on the insulating substrate 1; connection pads 25 and 27 arranged on unilateral ends of the wirings 23 and 24 and respectively connected therewit...

Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exp...

A solder ball structure having a first object and least one solder ball, each solder ball having an outer surface, top and a bottom and comprising a non-eutectic admixture of solder. The solder ball structure also having at least one BLM, each BLM having a top and a bottom and the top of each BLM in contact with the bottom of one of the at least one solder ball, each BLM containing a solder having a melting point sufficiently lower than the melting point of the corresponding solder ball such tha...