A parallel precoder circuit executes an EXOR operation on an n-row parallel input, and outputs an n-row parallel output, where 2.ltoreq.n. Outputs of EXOR circuits each of which having a largest column number from among EXOR circuits disposed in first to (n-1)th rows become first-row to (n-1)th-row parallel outputs, respectively. A output of an nth-row delay circuit becomes an nth-row parallel output.

Certain aspects of determining a signal quality metric in event of a CRC false positive may comprise measuring an amplitude and/or phase of at least a portion of a phase shift keyed section of a frame. The measured amplitude and/or phase may be checked to determine if it lies within a range of a reference amplitude and/or phase respectively. An amplitude and/or phase counter may be incremented if the measured amplitude and/or phase lies outside the range of the reference amplitude and/or phase r...

A method of decoding a turbo product code (TPC) code word comprises performing a cyclic redundancy check (CRC) on each of a plurality of code blocks of the TPC code word. The bits of code blocks of the TPC code word which pass the CRC are assigned an artificially high probability confidence measure, such as an artificially high log-likelihood ratio. Assigning these bits an artificially high probability confidence measure allows an iterative process, between a soft decision algorithm and a TPC de...

An RNIC implementation that performs direct data placement to memory where all segments of a particular connection are aligned, or moves data through reassembly buffers where all segments of a particular connection are non-aligned. The type of connection that cuts-through without accessing the reassembly buffers is referred to as a "Fast" connection because it is highly likely to be aligned, while the other type is referred to as a "Slow" connection. When a consumer establishes a connection, it ...

A channel encoding apparatus using a parallel concatenated low density parity check (LDPC) code. A first LDPC encoder generates a first component LDPC code according to information bits received. An interleaver interleaves the information bits according to a predetermined interleaving rule. A second LDPC encoder generates a second component LDPC code according to the interleaved information bits. A controller performs a control operation such that the information bits, the first component LDPC c...

A method of decoding possibly mutilated codewords (r) of a code (C) into information words (m') including information symbols (m'1, m'2, . . . , m'k), the information words (m) being encoded into codewords (c) of the code (C). In order not to considerably deviate from the standard method and apparatus for decoding a standard Reed-Solomon code, a method of decoding is proposed including decoding the possibly mutilated codewords (r) into codewords (r'), reconstructing information symbols (m'1, m'2...

A receiver employs iterative decoding of packet data, where the packet data represents a data frame encoded with at least two logical dimensions. A logical dimension refers to a layer, or sub-layer, of a layered network architecture. Consequently, a first logical dimension of encoding might refer to error detection in a packet frame at the data link layer, while a second logical dimension of coding might refer to error detection/correction encoding at a physical layer. For example, a data frame ...

Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which an LDPC coded signal is decoded by processing 1 sub-matrix at a time. A low density parity check matrix corresponding to the LDPC code includes rows and columns of sub-matrices. For example, when performing bit node processing, 1 or more sub-matrices in a column are processed; when performing check node processing, 1 or more sub-matrices in a row are processed. If desired, when perf...

An apparatus for reproducing information includes a memory unit which stores charge; a reading unit which obtains an amount of the charge stored in the memory unit, and reads information by determining a value based on a comparison of the amount of the charge with a first threshold; an error detection unit which determines whether the information read has an error; and a threshold generation unit which generates a second threshold having a value different from that of the first threshold used in...

Suitability of a recording medium for being recorded to and/or reproduced from by an apparatus is determined. Address information is read from a recording medium having at least a first area in which data is recordable, a second area, and a third area. The second area is followed by the first area which is followed by the third area. The address information includes first address information, which represents the position of the second area, and/or second address information which represents the...