A parallel processing apparatus capable of flexibly solving at a high speed the problem of synchronization wait when a plurality of tasks are generated, wherein a processor element PE12 specifies pipe counters and calls up a plurality of tasks with respect to processor elements PE13 to PE15 and waits for synchronization according to need by a synchronization wait command, an arbiter 56 increases a count value of a corresponding pipe counter when a task is called up and decreases the count value ...

A triology of methods to send, receive and execute are provided for JAVA process objects on client and server so that instance variables, rather than objects, can be transferred from/to client and server. In that manner, process objects at the server can be instantiated with instance variables from the client without object transfer. The system enables use of non-JAVA process objects at the server to perform functions at the request of a JAVA client.

A programmable arithmetic and logic unit (ALU) comprising a plurality of data selectors, the data selectors having corresponding data input lines; a plurality of ALU function input lines wherein the number of ALU function input lines is equal to the number of data input lines on each of the data selectors, and each ALU function input line corresponds to one data input line on each of the data selectors; wherein each of the data input lines of each of the data selectors is connected to the corres...

A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the...

A method and system for controlling the allocation of a data processing system's resources among two or more components competing for the resources. An internal system value is modified to yield a modified system value. A utilization history is created by mapping a component's utilization of the system resources. Then, the priority of the component is calculated utilizing the utilization history and the modified system value within a priority calculation.

A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an ...

A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIW) architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded ar...

The executing threads in CPU 100.about.103 are checked at random intervals in a specified range by interrupt execution modules 109.about.112, the results of the checks are stored in executing thread memory areas 113.about.116 and values of counters 117.about.120 that are corresponding to the executing threads are incremented. If the values of the counters 117.about.120 exceed specified values, applicable threads are judged to be operating abnormally and priorities of the applicable threads are l...

A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a plurality of execution units. An instruction and one or more operands issue into the instruction pipeline and a determination is made at one of the execution units whether the instruction is ready for execution. If so, the operands are loaded into the execution unit and the instruction executes. The exe...

A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and dete...