Selected domains, normally 2.times.10.sup.3.times.2.times.10.sup.3 such domains arrayed in a plane, within a three-dimensional (3-D) volume of radiation-sensitive medium, typically 1 cm.sup.3 of spirobenzopyran containing 2.times.10.sup.3 such planes, are temporally and spatially simultaneously illuminated by two radiation pulses, normally laser light pulses in various combinations of wavelengths 532 nm and 1024 nm, in order, dependent upon the particular combination of illuminating light, to ei...

A synchronous memory device which comprises global I/O lines for data input and output from and to a memory core and a pipeline latch circuit for latching data from the global I/O lines. The synchronous memory device includes a circuit that precharges the global I/O lines when a read command signal interrupts a write operation signal, and disables the pipeline latch circuit in order to prevent write data on the global I/O lines from being latched in the pipeline latch circuit. Accordingly, the w...

The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end...

A mask control circuit for generating an internal mask designation signal for masking read data includes a shift circuit incorporating and shifting an applied signal in accordance with an internal column related clock signal CLKD for transmission and a reset means responsive to inactivation of a clock activation signal defining a generation period of the internal column clock signal for resetting the shift circuit in an initial state. An output from the shift circuit is changed from the initial ...

The negative supply voltage used by the drivers during sector or chip level erase operations is decoded separately from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry coupled to the set of wordlines is provided. The wordline driver circuitr...

A test circuit for stress testing antifuses before programming. The test circuit provides a voltage to an antifuse detection circuit during antifuse stress testing. In one embodiment, the provided voltage is externally received at a probe pad. In another embodiment, the test circuit controls a voltage generating circuit output voltage from a normal operating voltage to a stress voltage, such as by shifting the ground reference for the voltage generating circuit. The stress voltage can be varied ...

A DRAM memory cell with improved data retention includes an access transistor, a capacitor, and a configurable voltage generator. The configurable voltage generator provides a cell plate voltage of 1/2VDD during an active mode and VDD during a non-active mode. The higher cell plate voltage during the non-active mode provides strong wordline disturbance immunity without negatively biasing the wordline. Because the wordline is not negatively biased, power dissipation caused by cross-fails are redu...

The object of the present invention is to provide a memory with reduced port area and excellent cost performance by combining a conventional multiport DRAM with a DRAM used as a temporary buffer, without losing the strong points of a conventional multiport DRAM, and in order to achieve that object, a memory of the present invention has a multiport DRAM and a general purpose DRAM having consecutive X addresses, common Y address and common control terminals, in order to promote efficient refresh c...

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting ...

A flash memory cell. The flash memory cell includes first and second transistors. The first transistor has a control gate coupled to a word line, a drain coupled to a data line and a floating gate. The second transistor, similarly, includes a control gate coupled to the word line, a drain coupled to a second data line and a second floating gate. The first floating gate stores a state of the second transistor prior to programming of the flash memory cell. Further, the second floating gate stores ...