A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied. The intern...

An ultra-low power, fast start fuze oscillator contained in a fast moving projectile which contains a programmable projectile fuze. It is an RC oscillator which uses a low power comparator, three biasing resistors, a timing resistor and a timing capacitor to produce an output frequency as low as 8 kHz with a frequency error of less than .+-.0.1% over a -40.degree. C. to +60.degree. C. temperature range. At the same time, it is capable of surviving a high g environment (30,000 g to 60,000 g) in a...

A multi-phase modulator for modulating n digital data into a 2.sup.n digital phase modulated signal includes digital-analog convertors for converting the digital data into analog signals, automatic gain compensators for controlling output levels of the analog signals, binary phase modulators for modulating the analog signals, a 90-degree phase shifter operatively connected to the binary phase modulators for providing modulated signals, the modulated signals being phase shifted from one another b...

A method and apparatus are provided for modulating a frequency synthesizer with an adjusted frequency control word determined by adjusting a carrier frequency control word based upon a bit content of a unsigned modulation control word. The method includes the steps of inverting a most significant bit of the unsigned modulation control word to produce an adjusted modulation control word and replicating the inverted most significant bit and appending the replicated bits to a most significant bit s...

Apparatus and method for estimating the angle-modulation imposed on a transmitted Radio Frequency (RF) or Intermediate Frequency (IF) carrier. The method estimates angle-modulation when communications channels add distortions such as noise to transmitted signals. The system provides reconstituted frequency modulation from a feedforward demodulator. The goal is to reduce the modulation index of a desired signal and to employ a narrower band-pass filter that passes this signal while rejecting the ...

A phase adjustment circuit includes a ring oscillator which is phase locked to an external pixel clock by a phase locked loop. The ring oscillator is formed of n number of stages of variable delay circuits providing n+1 outputs of substantially equal phase differences. A control signal generation circuit is responsive to a phase control signal to generate n+1 weighting coefficients for weighting the n+1 outputs from the ring oscillator in a weighting circuit which produces a phase adjusted outpu...

A system for synchronizing circuit operation within an integrated circuit having a high frequency clock. The system includes an oscillator for providing a clock signal and a transmission line coupled to the oscillator for distributing the clock signal to load buffers. The load buffers provide sub-circuits within the integrated circuit with synchronized clock signals. The load buffers are resonant and convert the capacitive load impedance of receiving circuits into a virtual inductive load. The i...

A system for measuring a phase difference between two input signals, including a computer performing computations in the complex domain and operating on two complex signals indicative of the two input signals respectively to compute the phase difference. Alternately, the system for measuring the phase difference includes a computer operating on two input buses indicative of the two input signals respectively to generate a signal indicative of the phase difference, and wherein: A. each input bus ...

A frequency synthesizer for generating two or more output frequency ranges using a Phase Locked Loop (PLL) circuit having a single voltage-controlled oscillator (VCO). In a first embodiment, a frequency multiplier is connected to the output of the VCO. The output of the VCO and the output of the frequency multiplier are selectably fed back, depending upon which output frequency is desired. The output frequency may be taken directly from the VCO or the frequency multiplier. When the output freque...

A quadrature oscillator based on two cross-coupled gm/C cells utilizes the inherent nonlinearity of positive and negative impedance cells to control the amplitude of oscillation, thereby simplifying the oscillator and eliminating the need for an outer control loop. The oscillator includes a pair of cross-coupled gm/C stages. A negative impedance cell is coupled to each gm/C cell for assuring proper start-up and enhancing the amplitude of oscillation. A positive impedance cell is also coupled to ...