A temperature detector comprises temperature sensing circuitry calibration circuitry, and power regular circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry interprets the temperature variation and outputs a value that represents the temperature. The power supply regulator circu...

In a reset mechanism for resetting a counter counting the number of rotations of a photoconductive drum which is employed in a laser beam printer and the like, rocking member is provided to be rocked only when the photoconductive drum is primarily rotated and means for resetting the counter in response to the rocking movement of the rocking member. Thus, the counter is accurately reset in case that a new photoconductive drum is installed in the printer and the photoconductive drum is primarily r...

A sample-hold circuit comprises a large number of sample-hold elements, and a multi-stage shift register for controlling sampling timings of the sample-hold elments, including a large number of stages corresponding to respective sample-hold elements, wherein each of stages of the multi-stage shift register includes an input gate for taking a signal shifted from the preceding stage thereinto, an output gate for shifting the signal taken in by the input gate to the succeeding stage, respective sam...

A portable apparatus suitable for use by a waitress for carrying money and making change which includes a signaling device for emitting a signal each time the apparatus is opened. The apparatus also includes a counter which counts and records the number of times the apparatus is opened.

An asynchronous nonlogical counting device includes at least a first counter and a second counter connected in cascade. The first counter has a frequency dividing ratio of 2.sup.n where n is a natural number. A control unit produces a control signal based on the count value of the first counter. The second counter has a variable frequency dividing ratio which is based on the control signal. The counting device can be made programmable by substituting a comparator circuit for the control unit. Th...

A universal shift register (200) utilizes a matrix (236-251) of high speed transmission gates to effect the various modes of register data manipulation in place of conventional operating mode selection logic gate elements. The shift register additionally includes apparatus allowing for the cascading of the register with units of similar design.

A frequency doubler operating where the predetermined duty cycle is essentially 50% in response to a series of input pulses with a given frequency and a duty cycle essentially of 50%. The circuit includes a means to generate a ramp signal which the ramp portion forms as a function of the repetition of the input pulses in response to the input pulses, an exclusive-OR logic to evaluate the exclusive-OR of the output from the ramp signal generating means and the input pulses in response to the outp...

A hyperfrequency dynamic divide-by-two frequency divider circuit includes an inverter stage A and a follower stage B, in which the output of the inverter stage is applied to the input of the follower stage via an interrupt transistor T.sub.1 which is controlled by the hyperfrequency input signal H having a frequency f.sub.e. The output Q of the follower stage B is fed back to the input of the inverter stage A and supplies the output signal having a frequency f=f.sub.e /2. The operation of the di...

A pseudokeyphasor signal control unit incorporated into apparatus for analyzing the vibratory behavior of a rotating machine in response to signals representing vibrations occuring in the machine, which apparatus includes: a controllable signal generator connected to receive an input signal representing the rate of rotation of the machine and to produce an output signal representing a rate of rotation bearing a selected relation to the rate of rotation represented by the input signal, the genera...

A clock generating circuit for use in a signal processing circuit to enable it to be synchronized with other circuits in response to a reset signal uses a multi-state circuit which is cyclically stepped through its states by a clock drive signal and a decoder responsive to the state of the multi-state circuit to produce the required clock pulses. The reset signal is used to stop the multi-state circuit at a particular state and hold it there for a period of time enabling other similar clock puls...