A transparent electrode for a gallium nitride-based compound semiconductor light-emitting device includes a p-type semiconductor layer (5), a contact metal layer (1) formed by ohmic contact on the p-type semiconductor layer, an current diffusion layer (12) formed on the contact metal layer and having a lower magnitude of resistivity on the plane of the transparent electrode than the contact metal, and a bonding pad (13) formed on the current diffusion layer. The transparent electrode is at an ad...

The semiconductor light generating device comprises a light generating region 3, a first Al.sub.X1Ga.sub.1-X1N semiconductor (0.ltoreq.X1.ltoreq.1) layer 5 and a second Al.sub.X2Ga.sub.1-X2N semiconductor (0.ltoreq.X2.ltoreq.1) layer 7. In this semiconductor light generating device, the light generating region 3 is made of III-nitride semiconductor, and includes a InAlGAN semiconductor layer. The first Al.sub.X1Ga.sub.1-X1N semiconductor (0.ltoreq.X1.ltoreq.1) layer 5 is doped with a p-type dopa...

An object of the present invention is to provide a positive electrode, in which the silver is used, for a compound-semiconductor light-emitting device high in inverse voltage and excellent in stability and productivity.The inventive positive electrode for a compound-semiconductor light-emitting device comprises a reflective layer of a silver alloy.

Variations in characteristics of transistors and a deterioration of a gate oxide film are reduced in a WP step. A method of manufacturing a semiconductor device of the present invention includes the steps of providing a SOI substrate having a semiconductor layer formed on a supporting substrate through a first insulating film, forming a plurality of SOI transistors on the SOI substrate, wiring the SOI transistors over a plurality of wiring layers, and providing electrical connection between the ...

Embodiments of an optical device including at least two transparent layers are disclosed.

The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.

A memory array having a smaller active area pitch is provided. In accordance with embodiments of the present invention, active regions are formed in a substrate and transistors are formed between adjacent active regions such that the active regions form the source/drain regions of the transistors. Word lines are formed perpendicular to the active regions and are electrically coupled to the gates of the transistors. Bit lines may be formed over the active regions to provide electrical contacts to...

The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first material on said surface portion of the third material. Then, an amorphous or partially crystalline second layer of the first material is formed on the at least partially crystalline fir...

A nitride-based light emitting device is manufactured by using a single-crystal nitride-based semiconductor substrate. A seed material layer is deposited on a first substrate where organic residues including a natural oxide layer are removed from an upper surface of the first substrate. A multifunctional substrate is grown from the seed material layer. The single-crystal nitride-based semiconductor layer including a nitride-based buffer layer is formed on the multifunctional substrate. The seed ...

The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.