A novel cache coherency protocol provides a modified-unsolicited (M.sub.U) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the M.sub.U state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified i...

A messaging scheme that accomplishes cache-coherent data transfers during a memory read operation in a multiprocessing computer system is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whethe...

A method and apparatus for managing heap memory for an application program in a data processing system. The system supports a basic addressing mode and an extended addressing mode. Programs operating in the basic addressing mode are limited to addressing using a first number of bits, program operating in the extended addressing mode are limited to addressing using a second number of bits, and the first number of bits is less than the second number of bits. One or more heap banks are established ...

In general, a system and method is provided for dynamically reallocating computer memory. A mapper receives requests to access data. The requests include bus addresses, and the mapper maps the bus addresses to memory unit addresses based on a plurality of mappings maintained by the mapper. The memory unit addresses identify a plurality of memory locations including a destination memory location and a source memory location. Data requested by the requests received by the mapper is accessed based ...

The virtual memory managing system of the present invention includes a virtual memory managing unit that manages a virtual memory system by combining swap-out in page units and swap-out in task units. The virtual memory managing unit includes: a memory area reserving unit that creates and manages swap management tables corresponding to a memory area reserve requests from tasks and reserves memory areas for the memory area reserve requests; a swap-out control unit that, when swap-out becomes nece...

A cache with a translation lookaside buffer (TLB) that reduces the time required for retrieval of a physical address from the TLB when accessing the cache in a system that supports variable page sizing. The TLB includes a content addressable memory (CAM) containing the virtual page numbers corresponding to pages in the cache and a random access memory (RAM) storing the physical page numbers of the pages corresponding to the virtual page numbers in the CAM. The physical page number RAM stores a p...

Load balancing of activities on physical disk storage devices is accomplished by monitoring reading and writing operations to logical volumes on the physical disk storage devices. A list of exchangeable pairs of logical volumes is developed based on size and function. Statistics accumulated over an interval are then used to obtain access activity values for each logical volume and each physical disk drive. A statistical analysis selects one logical volume pair. After testing to determine any adv...

A FIFO memory device for inputting/outputting data having variable lengths of the present invention, includes: a first holding portion for holding data having a maximum data length MAX of input data to be input to the FIFO memory device; a second holding portion for holding residue data having a data length shorter than the maximum data length; and an input selecting portion for selectively inputting the input data to the first holding portion and the second holding portion in accordance with a ...

Cache control protocols can be switched during running without changing an architecture for a segment descriptor or page descriptor for indicating an attribute of an area to be accessed. A plurality of processors each including a cache memory constitute a multiprocessor system which shares a main memory via a system bus. Each processor has module detecting means for detecting execution of a module which accesses a shared memory area on the main memory, by comparing the virtual space number and t...

In a data storage system that employs multiple storage drives to access removable data storage media, idle data storage media are analyzed and than selectively demounted by automated equipment to increase storage drive availability and also minimize unnecessary mount/demount operations. Initially, the system establishes a maximum permitted number of concurrently mounted idle storage media, and also establishes a maximum permitted length of time for leaving idle storage media mounted. Next, stora...