For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched aw...

An electrically erasable programmable read-only memory (EEPROM) comprises trench isolation regions whose upper surfaces are recessed compared with an upper surface of the semiconductor substrate, thereby allowing use of all surfaces of a protrusion of the semiconductor substrate between the isolation regions, including the upper surface of the semiconductor substrate, as an active region. Accordingly, the performance of a memory cell can be improved by increasing the size of an active channel re...

A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in throug...

The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of co...

A method of fabricating a thin film transistor array substrate is provided. First, a first patterned metallic layer, a dielectric layer, an amorphous silicon layer, a second patterned metallic layer and a passivation layer are sequentially formed over a substrate. A patterned photoresist layer is formed over the passivation layer. The patterned photoresist layer at least covers the source/drain (formed out of the first patterned metallic layer) as well as the area beside them. The edges of the p...

A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain ...

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is remo...

A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material...

A semiconductor device and method for fabricating the same. The semiconductor device comprises a capacitor including a semiconductor substrate having a first conductive type well; a first trench formed in the semiconductor substrate; a plate electrode formed on the first trench; a capacitor insulating film formed on the plate electrode; and a storage node electrode formed in the first trench. The transistor includes a first insulating film for planarization formed on the storage node electrode; ...

An organic EL display device includes an organic EL light emitting element having the first electrode, an organic EL layer and the second electrode formed on a substrate; and a color conversion filter bonded to the organic EL light emitting element and having a color conversion filter layer formed on a transparent substrate. An outer sealing wall and an internal filling portion are formed between the organic EL light emitting element and the color conversion filter. A partition wall is formed be...