Dielectric isolation in the bit-line direction is performed by a first trench filled with an insulator, dielectric isolation in the word-line direction is performed by a second trench filled with a conductive film serving as a field-shield electrode interposing an insulating film, and capacitors are formed on side walls of the second trench by the conductive film and a semiconductor substrate with the insulating film interposed therebetween. A high-density, large-scale DRAM is realized by combin...

A semiconductor device includes complementary first and second MOS transistors of different conductivity types and a bipolar transistor which are formed on a common substrate. The first MOS transistor has a first gate electrode of a polysilicon layer doped with impurities of a first conductivity type and a second conductivity type. A concentration of the impurities of the first conductivity type is higher than that of the second conductivity type. The second MOS transistor has a second gate elec...

A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

This semiconductor photodetector includes a photoabsorption layer, an n-type first semiconductor layer, and a p-type second semiconductor layer. The photoabsorption layer comprises an n-type first layer and a p-type second layer formed in contact with the first layer. The first semiconductor layer is arranged on the side of the first layer and has a shorter wavelength at a light absorption edge and a lower refractive index than in the photoabsorption layer. The second semiconductor layer is arra...

A method and structure are provided for an IGFET which has a short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Also the invention includes a dielectric layer with a high dielectric constant value (K) to prolong the longevity of the device. A lightly doped drain region similarly preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased ...

A MOS transistor comprising channel stoppers formed of a first polysilicon layer to determine a channel width, and a gate electrode formed of a second polysilicon layer, wherein a bias voltage is applied to the channel stoppers. In a charge detector having a source follower circuit with a drive MOS transistor and a load MOS transistor for converting a transferred signal charge into a signal voltage, the MOS transistor of the invention is used as the drive transistor, and its source output voltag...

A flash memory cell formed in a semiconductor substrate. The memory cell comprises: (a) a gate oxide formed atop said semiconductor substrate, said gate oxide including a thin region and a thick region; (b) a floating gate formed atop said thin region; (c) a control gate formed atop said thick region; (d) a drain region formed under said thin region and within said floating gate; (e) a source region formed under said thick region and outside said control gate; and (f) an insulating dielectric la...

A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows Fowler Nordheim (F-N) tunneling with lower absolute value bias potentials. Thus, the floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included...

Disclosed is a semiconductor layout design for use in integrated circuits that use balance circuitry. The semiconductor layout design includes a set of four substantially self enclosing gate transistors being arranged symmetrically about a common point. Wherein, each of the set of four substantially self enclosing gate transistors have a gate width that is defined by a perimeter around each of the set of four substantially self enclosing gate transistors. The semiconductor layout design preferab...

Metal alkoxycarboxylate-based liquid precursor solutions are used form electronic devices (100) that include mixed layered superlattice materials (112) of a type having discrete oxygen octahedral layers (124) and (128) collated with a superlattice-generator layer (116). The precursor solutions include a plurality of metal moieties in effective amounts for yielding the layered superlattice materials. These metal moieties are mixed to include an A/B portion capable of forming an A/B layer (124), a...