A non-volatile storage cell has (a) storage points which are insulated from one another and each having a stack of gates formed, in order, by a first insulant in contact with the substrate, a floating gate, a second insulant and a control gate, a source and a drain formed in substrate on either side of the stack and a channel, whose length is oriented in a direction (x) and (b) conductor lines serving to apply electric signals to the stacks of gates and the drains, the second insulant having, in...

Disclosed are measurement (observation) pads for judging whether or not a dynamic random access memory (DRAM) adopting a shared sense system is functioning as designed. Concretely, measurement pads are formed by the step of forming a second layer of wiring respectively connected to pairs of complementary data lines which are formed by the step of forming a first layer of wiring, and the signal waveforms of the pairs of complementary data lines are measured using the measurement pads. Further, th...

A programmable ROM is made up of a power source terminal, an internal power source voltage generator, a memory cell array, a memory cell drive circuit, and a data read-out circuit. The power source terminal receives a power source voltage of 5 V in a read mode, and a power source voltage of 12.5 V in a program mode. The internal power source voltage generator generates an internal power source voltage substantially equal to or lower than 5 V, on the basis of the power source voltage applied to t...

A memory card circuit for a portable memory card includes a unidirectional non-inverting buffer with an analog switch connected to an input terminal of a semiconductor memory and a bidirectional 3-state buffer with an analog switch connected to an input/output terminal of the memory card. An analog switch connected is series to a terminal signal of the semiconductor memory and a second analog switch connected in parallel to ground in parallel interfaces the card to a terminal unit. A transistor ...

In a method for programming an antifuse element which includes a pair of conductive electrodes separated by an insulating layer a predetermined number of voltage pulses are first applied across the electrodes of the antifuse and the current drawn by the antifuse is simultaneously measured. When the measured current indicates that the antifuse dielectric has ruptured, a second step includes continuing to apply pulses and calculating the difference in current sensed between successive measurements...

After passing through the process in which the number of one page I/O requests generated in a certain unit time period, the number of multiple pages I/O requests, and the number of pages required at each of the multiple pages I/O request are input, the quantity of the I/O requests generated in the above-described unit time period is calculated in accordance with the thus-input values. The unit (the number of pages) for a multiple pages I/O actually performed by one time operation of the I/O cont...

The described embodiments of the present invention provide a circuit and method for programming the mode options of an integrated circuit. The embodiment described provides this function for a dynamic random access memory but is applicable to any integrated circuit. The integrated circuit includes programming bonding pads which are either connected to a selected reference potential or left unconnected. Circuitry on the integrated circuit determines whether the pad is connected to the reference p...

A data protection system for protecting data stored in a memory in a data processing system having at least a channel system, a device controller and an external storage device. The data protection system includes a memory provided in the device controller which receives a power source voltage, and temporarily stores data to be transferred. A battery is connected to the power source and the memory, is charged by the power source when the power source is normal, and supplies a battery voltage to ...

A redundant circuit incorporated in a non-volatile memory device has two memory transistors for memorizing a bit of address information one of which is used in a diagnostic operation of component circuits executed before the packaging and the other of which is used for memorizing a bit of address information assigned to a defective memory cell after the packaging, and, for this reason, the other memory transistor is free from the degradation due to the heat attack encountered in the packaging pr...

A method and apparatus is disclosed for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next. A faster cycle type (e.g. page mode or static column) can thereby be employed in the Dynamic Random Access Memory (DRAM) memory by eliminating the DRAM precharge and RAS address portions of the cycle.