A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are preci...

A system and a method for synchronizing running disparity values in a first computer and a data demapping device are provided. The method includes generating a plurality of data characters and a synchronization control character. The method further includes iteratively determining a first running disparity value based on each character of the plurality of data characters and the synchronization control character. The method further includes encapsulating a first plurality of data characters and ...

A waveform acquisition system that captures and digitizes a wideband electrical signal through a bank of front end filters, frequency down converters, and conventional digitizers (A/D converters). A software algorithm reconstructs the composite input signal and applies the necessary corrections to remove the effects of hardware impairments. This approach is possible because it uses a class of filters that exhibit the quality of perfect waveform reconstruction, allowing signals whose spectral com...

The present invention relates to media data encoding devices. Embodiments of the present invention pertain to devices that receive media data, generate scalable media based on the media data, receive scalable attribute criteria, generate scalable profile data based, at least in part, on the scalable media and the scalable attribute criteria, and output the scalable profile data.

Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor i...

A signal converter such as a multi-channel pipelined signal converter includes a plurality of pipelined signal converters and a decision unit. Each of the pipelined signal converters has a respective plurality of stage cells coupled in series with switched coupling between the pipelined signal converters. The decision unit determines a respective selected path through the stage cells of the plurality of pipelined signal converters for each of a plurality of input signals during a signal path sel...

A sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator, and further providing increased tolerance of non-ideal integrators.

Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the rec...

Methods and apparatus are provided for interfacing a plurality of encoded serial data streams, such as Serial Gigabit Media Independent Interface streams, to a serializer/deserializer circuit. A plurality of encoded serial data streams are transmitted by receiving the plurality of encoded serial data streams that have been encoded using an encoding scheme that provides a substantially uniform distribution of a first code and a second code; marking at least one of the encoded serial data streams ...

A method for coding information in an electronic circuit and an electronic circuit for coding information uses at least two electrically coupled signal paths (X0, X1). Cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output si...