A method of manufacturing a semiconductor device includes the step of forming a capacitor. The step includes the step of forming a lower electrode constituted by a polysilicon film which selectively covers a surface of a predetermined insulating film on a semiconductor substrate, and the step of performing heating in an atmosphere containing an SiH.sub.4 gas and removal of a native oxide film on a surface of the lower electrode, and then performing formation of a silicon nitride film without bei...

A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (2...

A bipolar power device and a fast diode are formed in a single chip of semiconductor material. The chip contains a first area having high minority carrier lifetimes in which the bipolar power device is formed. The bipolar power device is therefore capable of handling high current densities. At least one second area of the device is formed with reduced minority carrier lifetimes, with a fast diode being formed in this region.

A method for producing a refractory metal gate electrode includes forming a patterning mask layer that is dissolved in a solution including hydrogen ions and having an aperture on a semiconductor substrate; forming a gate metal layer having an ionization potential larger than hydrogen on the entire surface of the patterning mask layer; forming a low resistance metal layer of a predetermined configuration having an ionization potential smaller than hydrogen on the gate metal layer; covering at le...

A method for fabricating a thin film transistor includes the steps of: forming a semiconductor layer and a gate electrode on an insulating substrate with a gate insulating film interposed therebetween; and implanting an impurity element into a surface of the semiconductor layer by accelerating hydrogen ions and ions of an element of the group III or the group V of the periodic table using at least one of the gate electrode and a resist mask used for forming the gate electrode as a mask, so as to...

The present invention is mainly characterized in that a Bi-CMOS is obtained in which characteristics of a bipolar transistor are not deteriorated. The device includes a bipolar transistor and a CMOSFET formed on a semiconductor substrate separately from each other by a field oxide film. The thickness of a gate electrode of an NMOSFET and a gate electrode of a PMOSFET is made larger than the thickness of an emitter electrode of the bipolar transistor.

This invention provides a method of forming contact holes and via holes in interlevel dielectric which insure good metal stepcoverage. The contact or via holes have tapered sides and smoothed edges. The method uses isotropic etching, anisotropic etching, and argon sputter etching in vacuum and does not require high temperature contact reflow. The final argon sputter etch is a timed etch that smoothes all sharp edges, exposes the regions where electrical contact will be made, and planarizes the i...

A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conductivity type to form an emitter (30) and a collector (32). The portion of the tub (22) between the emitter (30) and collector (32) regions forms a base region. This configuration provides high emitter area and minimal device surface area, as well ...

A vertical Triple Heterojunction Bipolar Transistor (THBT) and method of fabrication therefor. The THBT collector has a substrate layer of N.sup.+ silicon, an N.sup.- silicon layer grown on the substrate and a Si/SiGe superlattice grown on the N.sup.- silicon layer. The THBT base is layer of P.sup.+ SiGe grown on the superlattice. The THBT Emitter is a second Si/SiGe Superlattice grown on the base layer. An N.sup.- silicon layer is grown on the emitter superlattice. A layer of N.sup.+ GaP grown ...

A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provid...