A data communication system which includes a data distributor, a communication station and a plurality of front-end-processors. These front-end-processors are connected with a computer through a common bus. The distributor distributes the data received by the station to one available front-end-processor, which preprocesses the received data, and transfers the pre-processed data to the computer through the bus. By operating the front-end-processors in parallel with respect to successively receive...

A programmable sequence control apparatus including a first memory device for storing sequence program instructions, an input/output device, a relay ladder operation device for executing logic operations for a relay ladder circuit having n rows and m columns (wherein n and m are positive integers) in accordance with the program instructions, and a control device for delivering control signals to the relay ladder operation device, is so constructed that the control device includes a memory device...

There is described a unique apparatus for exchanging commands and data via a dedicated memory which has ports connected to the data and address busses of two different microprocessors. The system operates even though the microprocessors have different word lengths, e.g. a sixteen bit processor and an eight bit processor. The system permits interfacing between the microprocessors with different bit size words and allows each of the microprocessors to treat the exchange memory as part of its own m...

A system for use in an electronic digital signal processor for assembling multiple report definition instructions to create a shell document to generate a file report. The system enables an operator to depress an instruction key to call up an instruction menu and select for display the report definition instruction menu. The operator chooses report instructions desired in any order, and the system inserts chosen instructions in proper order to build the shell document. The operator keys report i...

This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via ...

A microprogrammed data processing system is provided in which each high level instruction is performed by one or more tasks, each task being in turn performed by executing one or more task microinstructions in a microprogrammed manner. Dynamic resource allocation is provided by employing a plurality of dynamically allocatable registers whose free and use states are continuously monitored in an allocation register. The outputs of the allocation register are used as an address for a register alloc...

The disclosure describes improved apparatus for transferring data from the main memory of a data processor to a peripheral permanent storage unit, such as a data recording holder driven by a driving device, in response to a failure of the main electrical supply to the data processor. The apparatus includes frequency converters for supplying voltage to the processor for about 500 milliseconds after the power fails. Logic and selector circuitry reads the contents of main memory into a selected per...

A system for the electronic control of a multi-system machine, or for the manufacture of control strips for textile machines containing a storage system for color lines which are obtained by scanning a multi color design pattern and which contain in series form information about a given color of a standard design, and a storage unit inserted after the storage system for the continuous control of each system by step-wise read-out of the stored color lines, the system having the improvement of a s...

This specification describes an associative memory decoder for a memory system in which the units in the memory system are reconfigurable both in size and in number. The decoder is designed to take an address for that memory system and address memory space in the memory system irrespective of the amount of storage in the system so that the decoder has to change as memory capacity is added or subtracted from the memory system.

Disclosed is a data processing system which operates with multi-programming and virtual storage. Logical addresses are translated to real addresses by use of translation tables stored in main storage. Each program has its own unique translation table. A buffer memory, including a high-speed logical translation store, stores real addresses which have been translated from logical address by use of the tables. A program identifier store identifies what programs have translated information within th...