In a CAM having valid cells, an idle word is detected and outputted by using the data in the valid cells and an address encoder. A detection circuit of an idle word for a content addressed memory having valid cells 15, which includes a unit 19 for supplying the output (valid 16) of the valid cell 15 to an address encoder 18 in response to an idle word detection signal IWD.

A controller interrupts and restarts writing data from a buffer memory to a medium and prevents buffer underrun errors. The controller includes an address memory for storing a recording medium address or a buffer memory address, which indicate the location of the data when the interruption occurred. A synchronizing circuit sequentially reads data from the recording medium and data from the buffer memory prior to the interruption while synchronizing the written data and the stored data. A restart...

A method of forming a hashing code includes the steps of: first selecting a first linear feedback transform generator that is perfect over a first range. A maximum key length is determined next. When the maximum key length is greater than the first range for a transform, it is determined if a no collisions allowed condition exists. When the no collisions allowed condition exists, it is determined if the maximum key length is less than double the first range. When the maximum key length is less t...

A CAM providing for the identification of a plurality of multiple bit tag values stored in the CAM, having logic circuitry for comparing each bit of an inputted test value to the corresponding bits of all stored tag values. A bit select is employed for generating a plurality of test bits for sequential input into the logic circuitry. The logic circuitry compares the plurality of test bits to the corresponding bit of each stored tag value and generates a "hit" signal if the selected bit is the sa...

A method and apparatus are provided for scheduling commands for random access storage devices with a shortest access chain scheduling algorithm. A plurality of possible chains for a queue of commands are processed. The plurality of possible chains are compared to identify one of the plurality of possible chains having a predetermined property. A first command of the identified one chain having the predetermined property is selected as a next command to execute. The predetermined property include...

A multiple agent system providing each of a plurality of agents, i.e., processors, access to a shared synchronous memory. A super agent is preferably that agent from among a plurality of agents which accesses a shared synchronous memory most frequently. The super agent has direct access to the shared synchronous memory, without negotiation and/or arbitration, while the non-super agents access the shared synchronous memory under the control of an arbiter-and-switch. Open windows are generated whe...

Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory...

A buffer output manager facilitates automatic self-triggering output of buffer contents. At least one processes writes control data to at least one buffer, the control data being such that a buffer output trigger address can be determined therefrom. For each buffer to which control data is written, a buffer output manager determines the trigger address of that buffer. At least one process writes data to at least one buffer, including to the trigger address thereof. For each buffer to which data ...

Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phas...

A method of migrating data from an old storage subsystem to a new storage subsystem in a data processing system which comprises host computers and storage subsystems. There is provided a route-changing phase before the data is migrated from the old storage subsystem to the new storage subsystem. In the route-changing phase, each host computer can access both the old and new storage subsystems and the new storage subsystem writes data into the old storage subsystem in response to a write request ...