A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. The microprocessor can access the auxilary chip to ascertain the power history. That is, the microprocessor can direct an interrupt to the auxilary chip, which will cause the auxiliary chip to respond with a signal which indicates to the microprocessor whether the power supply voltage is heading up or down. When ...

The present invention is a method, system and process for automatically customizing a computer environment based on the current active computer disk directory. Detection of the current active disk directory and any change of disk directory by a user triggers a search for a file that initiates the computer environment. Upon detection of the file, the system reconfigures the operating system to meet the user's requirements based on the disk directory.

The disclosed invention is directed to a computer system comprising a log-on device, which at log-off records information defining the user's activity (e.g., the user's view of objects displayed on his display terminal), and, at log-on, automatically restores the system to the situation extant at log-off. The storage device on which the object view data is stored is removable, whereby the user may carry it from one terminal to another.

The chip architecture of an MOS microprocessor chip includes data bus input-output buffer circuitry located along the lower right hand edge of the chip. High order address buffer output circuitry is located along the bottom of the chip. Directly to the left of the data bus input-output buffer circuitry is the arithmetic logic unit circuitry, and to the right of this and adjacent to the high order address bit buffer circuitry is located a register section including first accumulator register, a s...

The disclosure describes improved microprogramming apparatus for a data processor. The improved apparatus includes a translating diode matrix which translates the operation code of a macroinstruction being executed into a predetermined address of a microinstruction stored in a read-only memory. For each operation code being executed, the translating diode matrix is capable of reading two different microinstructions held at two different addresses. This technique enables the sharing of microinstr...

A machine which classifies objects on the basis of an analysis of certain features related to that object, an example of which is a blood cell analyzer/counter, is subject to a number of random errors in recognition, which errors on the average tend to appear as a systematic bias. A correction device corrects for these errors to provide a more accurate count.

An apparatus for performing efficient transposition exchange sorts among equal length records is described. The apparatus takes advantage of the flow steering property of linkable circulating storage loops to minimize the average access time by positioning information closer to the output port in a storage structure. The apparatus is formed from a linear array of equal size shift register loops each holding one record. The loops are switchably interconnected such that when two boundary switches ...

In an input/output data processing system employing local and remote memory and paged data storage, memory steering is included in the address development, thus eliminating the need for special memory configuration logic. Words used in constructing absolute memory addresses for data fetches include address portions referencing local/remote memory, specific memory, and/or lack of memory residence for effecting a system fault procedure.

Method for the conversion of a frequency into a number, characterized in t use is made of a reversible counter driven by a logic control circuit receiving clock pulses and a frequential input signal formed by pulses having a period of a in addition to a stochastic feedback signal representing the required number, where the required number is a number which depends on the frequency of the input signal and is generated by this method. The logic control circuit makes the counter count up the clock ...

In a data processing system which includes a common bus to which a plurality of units are connected for the transfer of information, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a split bus cycle operation in which the master unit requesting information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a later slave generated ...