A high bandwidth emitter-coupled logic (ECL) circuit is provided. The ECL circuit comprises an emitter-follower circuit with first and second transistors having collectors connected to a first power supply (Vcc), and emitters operatively connected to a second power supply (Vee2) approximately 1.5 volts less than the first power supply. The transistors receive differential input signals from an interfacing CML circuit. In some aspects, the first power supply is 3.3 volts and the second power supp...

Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency p...

An extended voltage range level shifter is provided that includes an input inverter and first and second circuit branches. The input inverter includes thin-gate devices, is coupled to an internal power supply, and is operable to receive internal data and to generate inverted internal data. The first circuit branch includes a p-type, thick-gate transistor that has a source coupled to an external power supply; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type ...

Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of configurable metal for routing. The extra semiconductor area in the cells of a metal limited device is used to implement general purpose RAM. Common select lines and read/write lines for the RAM are embedded in the base cells so that the configurable metal (whether via or actual metal layer) over the RAM can ...

Clocked full-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off d...

A method and device to emulate impedances includes a pair of impedances connected in series between two circuit nodes, the impedances forming a voltage divider having at its midpoint a reference voltage V.sub.X. An OP AMP includes a positive input connected to the V.sub.X.sub..sub.-- node and the negative input connected to the output thereof in a direct feedback loop. The OP AMP output is also connected to a load impedance that is connected either one of the nodes. A transistor may be interpose...

An integrated circuit comprises plural superconducting circuit blocks connected through superconducting wiring strips, and each superconducting circuit block includes at least one superconducting logic circuit, constant input/output circuits connected between the input/output nodes of the circuit block and the superconducting logic circuit; parameters of the constant input/output circuits are regulated such that statically flow-in/flow-out current is approximately equal to zero at the input/outp...

An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.

In order to prevent filter characteristics from being deteriorated due to generation of a spurious pulse is unnecessary resonance at a high level in a passing band at the frequency in a microwave region used in a portable telephone system or the like, at least two types of dielectric resonators having different frequency characteristics in unnecessary harmonic modes except for a main mode near the passing band of a filter are arranged in spaces partitioned by partition walls in a shielding unit ...

A differential latch includes a sample transistor section, a hold transistor section, a 1.sup.st gating circuit and a 2.sup.nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., V.sub.DD and V.sub.SS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1.sup.st gating circuit is operab...