A semiconductor device has a substrate composed of a semiconductor which has one of sphalerite and diamond crystal structures. The substrate has a plane orientation inclined at 0.5.degree. to 15.degree. with respect to one of {111} and {110} planes indicated by Miller indices. A first semiconductor layer is formed on the substrate. The first semiconductor layer has a sawtooth-shaped first periodic structure consisting of one of the {111} and {110} planes indicated by the Miller indices and at le...

A charged coupled device structure (CCD) and a method for fabricating the CCD structure, which induces a maximum potential distribution difference by utilizing gate insulation films having different physical properties. The charged coupled device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a plurality of first electrodes spaced at fixed intervals over the first insulation layer, a second insulation layer formed only between the plurality of...

An amorphous semiconductor thin film light emitting diode comprising of a first electrode metal sheet substrate, amorphous semiconductor layers and a second optically transparent electrode. The first electrode metal sheet substrate acts as the support of the electrode and provides ruggedness, good thermal stability and dissipation of heat, good reflectance and flexibility. The device may further include electrically insulating layers which cause a pattern of light to be emitted by the diode, by ...

SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction. SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.

Lead-over-chip leadframes for coupling chip bond pads to the pins of a memory package contain a first plurality of short leads for coupling data chip bond pads to data pins on a first side of the memory package; a first plurality of long leads for coupling data chip bond pads to data pins on a second side of the memory package; a second plurality of short leads for coupling address chip bond pads to address pins on the second side of the memory package; and a second plurality of long leads for c...

A thin-film heat sink comprises a heat sink film functioning as a heat sink and a bonding film for bonding the heat sink film to a base. The bonding film is an aluminum oxide (Al.sub.2 O.sub.3) film formed using the CVD method and the heat sink film is an aluminum nitride (AlN) film. For the AlN film as the heat sink film, internal stress is compressive stress, whereas for the Al.sub.2 O.sub.3 film as the bonding film, internal stress is tensile stress.

A high temperature hybrid-circuit structure includes a temperature sensitive device which comprises SiC, AlN and/or Al.sub.x Ga.sub.1-x N(x>0.69) connected by electrodes to an electrically conductive mounting layer that is physically bonded to an AlN die. The die, temperature sensitive device and mounting layer (which can be W, WC or W.sub.2 C) have temperature coefficients of expansion within 1.06 of each other. The mounting layer can consist entirely of a W, WC or W.sub.2 C adhesive layer, ...

The solar cell of the present invention includes a titanium dioxide semiconductor that is held between a pair of electrodes so that the titanium dioxide semiconductor and at least one of the electrodes form a rectification barrier.

A sensor formed in a substrate of a first conductivity type in a first concentration to express a first intrinsic potential includes CMOS circuitry to control the sensor, a first well of the first conductivity type in a second concentration (greater than the first concentration) formed in the substrate to express a second intrinsic potential, and a photodiode region of a second conductivity type formed in the first well. The first and second intrinsic potentials induce a field between the substr...

An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop...