A testability architecture and method for loosely integrated (modularized) integrated circuits uses stand alone module testing. For an integrated circuit chip which has a number of independent modules, where one module design is used in a number of different chips, each module is connected to the chip's input/output pins and to a configuration module. To make testing of the modules more efficient and less expensive, during testing of the chip a particular module design is confronted with the sam...

An on-chip monitoring circuit is composed of a plurality of individually addressable nodes that are connected together in a circuit which extends from an external data port to each of the monitored circuit points. Address and enable information is passed from node to node. Each node contains address decoding circuitry and enable generation circuitry. As a node receives address information, it decodes part of the address information and enables some of the nodes connected to it, passing the remai...

A recording/reproducing apparatus is provded for dispersedly recording one-frame data on a plurality of tracks. The recording/reproducing apparatus includes a trans-codec for format converting received digital data into sync blocks each of which has a predetermined size and converting the sync blocks into a format possessed by the received digital data, a frame error corrector for interleaving data of the sync blocks allocated on different tracks in each frame using the sync blocks supplied from...

A high speed link between chips and comprising a multiplicity of synchronous serial data channels includes an onboard detector for detecting an error rate for each channel. The transmitter and the receiver chips are configured in response to the detector to select the channel having the lowest error rate as the control channel and optionally to render at least the channel with the highest error rate inactive.

A Data Link Layer (DLL) protocol for direct support of the Internet Protocol (IP) networking in the Universal Mobile Telecommunications System (UMTS), is provided. The disclosed Data Link Layer comprises a Radio Link Control (RLC) sublayer and a Medium Access Control (MAC) sublayer. At a transmit end, as well as at a receiving end of the UMTS wireless system, a plurality of Quality of Service (QoS) planes are created according to IP QoS requirements. At the RLC level, each QoS plane comprises a ...

The present invention provides a system and method for the time-varying randomization of a signal stream to provide for a robust error recovery. A current block of data is randomized in accordance with data from the current block and data from at least one temporally adjacent block of data. The present invention also provides a system and method for time-varying derandomization of a randomized signal stream and alternately delayed-decoding of the signal stream. Randomized data is derandomized us...

A node controller (12) includes a local block unit (28) that receives and processes request and reply packets. A request module (30) in the local block unit (28) receives a request packet and determines whether the request packet has an error. If there is no error, the request module (30) forwards local invalidation requests to a invalidation module (32) for processing and forwards programmed input/output read and write requests to a processor module (34) for processing. If an error is detected,...

Where a number n of read attempts are required to successfully read a data sector, with the first n-1 attempts returning a disk drive read error, the number of attempts required is compared to a predefined threshold selected to indicate that the sector is unreliable and is in danger of becoming completely unrecoverable. If the threshold number of attempts is not exceeded, the sector is presumed to still be good and no further action need be taken. If the threshold number of attempts was equaled ...

First, in the step of analyzing integrated circuit information, integrated circuit information is retrieved and the structure of the circuit is analyzed, thereby creating routing information for each functional block. Next, in the step of analyzing pin allocation information, pin allocation information, including input and output pin connection information for the functional block, is retrieved and the contents thereof are analyzed, thereby creating machine-readable pin combination information. ...

A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An...