Provided is a method of manufacturing a ferroelectric capacitor capable of manufacturing a ferroelectric capacitor with lower unevenness on a ferroelectric film surface, and thereby with excellent electric characteristics. By sputtering method, a PZT film is formed on a first conductive film, which constitutes a lower electrode of the ferroelectric capacitor. Thereafter, the PZT film is subjected to crystallization treatment (annealing). Next, a silicate solution is coated on the PZT film as a s...

A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions...

An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Disclosed is a reflection type liquid crystal display (LCD) and a manufacturing method thereof. A first substrate on which a pixel array is formed is prepared. A second substrate is formed facing the first substrate. A liquid crystal layer is formed between the first and second substrates. A reflective electrode is formed on the first substrate. The reflective electrode includes a plurality of first regions and a plurality of second regions having a height difference relative to the first region...

A method for making a self-aligned isolated memory core for a flash memory wafer includes the steps of establishing control gates for memory cells in the core by depositing a first polysilicon layer on a silicon substrate, etching the first layer, and depositing a second polysilicon layer on the substrate, with the polysilicon layers being separated by an interpoly dielectric layer. Then, after the control gates have been established, isolation trenches are formed in the silicon substrate betwee...

Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. ...

A layered structure comprises a variable wettability layer including a material that changes a critical surface tension in response to energy provided thereto, the wettability changing layer including at least a high surface energy part of large critical surface tension and a low surface energy part of low critical surface tension, a conductive layer formed on the variable wettability layer at the high surface energy tension part, and a semiconductor layer formed on the variable wettability laye...

A semiconductor light emitting apparatus comprises: a semiconductor light emitting device; resin that seals the semiconductor light emitting device; and antireflective coating provided on a surface of the resin. The antireflective coating is made of material having an intermediate refractive index between the refractive index of the resin and the refractive index of air.

The likelihood of exfoliation of a sealing resin layer at a pad electrode part is reduced so that the reliability of a circuit apparatus is improved. A circuit apparatus includes a wiring layer, a gold plating layer, an insulating resin layer, a circuit element, a conductive member and sealing resin layer. The gold plating layer is formed in an wiring layer area for the pad electrode. The surface outside the area is roughened. The insulating resin layer is formed so as to cover the wiring layer ...

A novel method for synthesizing device-quality alloys and ordered phases in a Si--Ge--Sn system uses a UHV-CVD process and reactions of SnD.sub.4 with SiH.sub.3GeH.sub.3. Using the method, single-phase Si.sub.xSn.sub.yGe.sub.1-x-y semiconductors (x.ltoreq.0.25, y.ltoreq.0.11) are grown on Si via Ge.sub.1-xSn.sub.x buffer layers The Ge.sub.1-xSn.sub.x buffer layers facilitate heteroepitaxial growth of the Si.sub.xSn.sub.yGe.sub.1-x-y films and act as compliant templates that can conform structura...