A signal-processing apparatus has a digital filter for processing input data from a knock-sensor. The digital filter is designed as an FIR filter characterized by filter coefficients that are equal to values of mince points 0 to 16 obtained based on a reference waveform. The reference waveform is created by concatenating half waves of a first sinusoidal waveform with half waves of a second sinusoidal waveform with peak values equal to half the peak value of the first sinusoidal waveform. The val...

An integrator with a reset mechanism comprises an integration capacitor and a replacement integration capacitor, wherein the integration capacitor is replaced with the replacement integration capacitor during a reset operation. A method of resetting an integrator comprises temporarily removing an integration capacitor and replacing the integration capacitor with a reset capacitor during a reset operation of the integrator. The method may further comprise temporarily removing the integration capa...

Methods and apparatuses for run length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor in response to the microprocessor receiving a single instruction includes: receiving a first list of a plurality of elements from a first vector register; generating a plurality of run values respectively for the first list of elements, at least one of the plurality of run values indicating the number of consecutive elements of a first value i...

In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, 1/2 of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

An arrangement for interpolating signals interpolates an analog measured signal which is dependant on a measured variable and which is fed to a voltage divider whose pickoff signals are fed to comparators from whose output signals the interpolated measured variable is determined. In order to reduce cost, the pickoff signals are fed by switches to comparators whose number is smaller than that of the pickoff signals. In this process the switches must connect the pickoff signals to the comparators ...

A first D/A converter generates first and second reference voltages from digital data of upper m bit by using base reference voltages of these reference voltages. A controller outputs a control signal according to which of voltage levels of the first and second reference voltages is higher. An inversion controller outputs digital data of lower n bit as such to a second stage R-2R ladder resistor type D/A converter when judging that the first reference voltage is higher in voltage level than the ...

An integrated circuit for generating targeted bitlength manipulation of a transmitter for output of a serial datastream. A control unit (5) provides instructions regarding respective partial bits in a form of a partial bit vector (7) depending on bit statuses to be sent, and determines bitlengths for the serial datastream for output (9) to a wire or a signaling converter. The datastream (9) is generated using two partial bit register chains (14a-d, 15a-d), whose serial outputs (16, 17) are conne...

A maximum length (M) of compressed codes desired to be decoded in a single lookup is determined. 2.sup.M rows are generated, with each row having a bit indicating whether a corresponding M-bit combination, when viewed from the first bit, contains a compression code and a source code corresponding to the compression code. A matching row corresponding to a value represented by M-bits of a source bit stream ("present portion") is first determined, and the source code in the matching row is set as t...

The present invention relates to method and apparatus of converting a series of data words into modulated signals. This method generates for each data word a number of intermediate sequences by combining mutually different digital words with that data word, scrambles these intermediate sequences, translates each scrambled sequence into a (d,k) constrained sequence, detects running digital sum (RDS) every bit for each translated (d,k) constrained sequence while counting sign changes of each RDS, ...

A digital-to-analog converter (DAC) output stage has an operational amplifier, an integrating path, a direct or data path, and a differentiated path. The integrating path is coupled in parallel to the operational amplifier. Each of the ends of the integrating path is respectively coupled to an input and an output of the operational amplifier. The direct or data path samples data during a first time sampling phase and is coupled in parallel with the integrating path during a second time sampling ...