
In one embodiment, a processor comprises a cache shared by a plurality of threads in execution by the processor, an error detection unit coupled to the cache, and a fetch control unit. The error detection unit is configured to detect an error in data output by the cache responsive to an access corresponding to a first thread of a plurality of threads. Coupled to receive an indication of the error, the fetch control unit is configured to inhibit fetching for the first thread responsive to the err...











