A powder feeding assembly for feeding a flame-melting device is disclosed. The powder feeding assembly includes a powder holding chamber with a screening member and a brush assembly disposed therein. The brush assembly includes at least one bristle element having a distal and a proximal end. The distal end is disposed proximate to the screening member. Powder held in the powder holding chamber is urged through one or more openings in the screening member by rotating the brush assembly. The powde...

An edge aligner/holder 10 having an edge aligner 30 with a resilient front end 32 and a tail piece 34 cooperatively interengaged with a reciprocating mechanism 36, and having a holder 20 with at least one rest 23 and one backstop 24, the holder 20 mounted above said front end 32 on said edge aligner 30. The resilient front end 32 of the edge aligner 30 holds a job stack 2 containing sheets which already have been piled in alignment when the edge aligner 30 is in its forward position, while at th...

A metering device for plastic materials comprising a bin having a rotating feed disc at the bottom thereof. The feed disc has peripheral cogs which partially define a metering chamber. Facing the metering disc is an ejection disc having teeth meshing with the cogs for forcing material into the metering chamber and ejecting the material from the metering chamber through an opening in the side of the bin.

The present invention is particularly directed to the enabling of a refresh cycle for a dynamic memory chip at a period in the fetch cycle, for example, of a type 8085 microprocessor, when the normal timing of the chip does not permit addressing of the memory. Specifically, in the fetch cycle, a fourth clock period occurs following a memory read pulse. This fourth clock cycle is required for the application of the microprocessor, but does not involve any addressing of the memory. Accordingly, in...

This invention involves a capacitor memory cell (C.sub.S) of, typically the metal-oxide-semiconductor (MOS) capacitor type, which is accessed for reading and writing by means of an access network connected to the memory cell through a gating transistor (T.sub.1), and which is provided with an independent refresh network for maintaining the memory state of the cell in the absence of an access writing signal. The refresh network includes a pair of MOSFET (Metal Oxide Semiconductor Field-Effect Tra...

A circuit to permit testing the refresh counter in an integrated circuit memory by writing into cells whose row addresses are determined by the refresh counter.

An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock...

The dynamic RAM has a refresh circuit with two operation modes. In the first operation mode, a variety of signals necessary for the refresh operation are formed in the dynamic RAM. Accordingly, the refresh operation of the dynamic RAM is performed completely automatically. As long as the refresh operation is being carried out, a busy signal is produced from the dynamic RAM to prevent an erroneous writing operation or reading operation. In the second operation mode, the refresh operation of the d...

A dynamic semiconductor memory device having a refresh-address generator, includes an initial resetting circuit for resetting the output signals of a refresh-address counter when the power supply is turned on, thereby eliminating the need for counter checking procedures prior to the examination of the refresh-address generator.

A dynamic random access memory (DRAM) device is formed on a semiconductor substrate, the device having an array of memory cells which are divided in several sub-arrays. The device has memory blocks each containing one of the sub-arrays, a word decoder and column decoder. Each of the memory blocks is selected independently to perform an access operation and refresh operation. As long as different memory blocks are selected for the respective operations, both operations are performed in parallel, ...