A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The con...

A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instru...

High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, sig...

The invention relates to a combined handle and spout for a liquid containing vessel and where such handle and spout are formed as a unitary member.

A method and apparatus for converting a packed integer data item having first and second data elements, to a packed floating-point data item. In one embodiment, a method includes moving the first data element of the integer data item to a first data element of a first intermediate data item and extending a sign of the first data element into all bit positions of a second data element of the first intermediate data item. The method further includes moving the second data element of the integer da...

An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction from another one of the plurality of threads. The processor may also include floating-point arithmetic logic configured to execute a floating-point instruction issued by the instruction fetch logic from a given one of the plurality o...

A preloadable floating point unit includes first and second preload registers that hold a next operand and a next top of array (TOA) for use with a next FPU instruction held in an instruction queue pending completion of the current FPU instruction.

A novel fluid container system comprises a container having a port at an upper end through which port fluid is permitted to pass for emptying the container. A restricter is provided within the container for momentarily restricting fluid flow out of the port when the container is inverted, the restricter having a construction such that a restricted fluid flow is permitted through the port for a period of time when the container is inverted, after which period of time a substantially less restrict...

Assembly for dispensing product of pasty fluid consistency, which includes a container (2) made of flexible material containing the product and a dispensing head which includes a dome (3) and is equipped with at least one dispensing orifice (4) capable of being closed by a movable stud (7) carried by an elastically deformable membrane (6), the container (2) and the dome (3) constituting a single piece obtained by moulding, a rigid insert (5) being put into position at the base of the dome (3) an...

A microprocessor configured to dynamically switch its floating point load pipeline length from one stage in length to more than one stage in length is disclosed. The microprocessor may perform normal loads and detect denormal loads in a single clock cycle. The microprocessor temporarily stores each scheduled floating point instruction in a reissue buffer for at least one clock cycle. When a denormal load instruction is detected, the microprocessor is configured to add one or more stages to the f...