In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be ...

To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO.sub.2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO.sub.2 does not inclu...

Access transistors of memory cells in a DRAM are formed in a solid phrase epitaxial single crystalline layer on the surface of a silicon substrate. A bit line extending over the surface of an element isolation and insulation film is formed by patterning a polycrystalline silicon layer extending to the single crystalline silicon layer as a layer. A stacked capacitor is connected to one source/drain of the access transistor through a conductive layer extending to the single crystalline silicon lay...

A thin film semiconductor device comprising a thin film transistor (TFT) having a thin film semiconductor on an insulation substrate to define an element region, and a hygroscopic interlayer insulating layer which covers said element, a hydrogenation treatment which comprises said interlayer insulating layer provided thereon a capping layer for blocking hydrogen diffusion, so that water entrapped by the interlayer insulating layer may be decomposed to generate hydrogen which is allowed to diffus...

In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be ...

A method of manufacturing a semiconductor device is provided. The method includes providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type. An opening is formed penetrating the device isolation region and the embedded insulation layer and reaching the semiconductor substrate. A polys...

A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a back gate region is formed separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layer. ...

A semiconductor device including a transistor having an SOI structure the operating speed of which is not affected is provided. A MOS transistor having the SOI structure is formed which satisfies RCf<1 where C is a gate capacitance (F), R is a body resistance (.OMEGA.), f is a clock operating frequency (Hz), and f.gtoreq.500 MHz.

An insulated gate semiconductor device comprising an insulator substrate having provided thereon a source and a drain region; a channel region being incorporated between said source and said drain regions, said channel region comprising a polycrystalline, a single crystal, or a semi-amorphous semiconductor material; and a region provided under said channel region, said region comprising an amorphous material containing the same material as that of the channel region as the principal component, o...

A preventive treatment method for a multilayer semiconductor wafer is described. The semiconductor wafer includes a supporting substrate, at least one intermediate layer and a surface layer in which an intermediate layer has an exposed lateral edge and the wafer is to be subjected to a subsequent treatment. The method includes encapsulating the exposed lateral edge of the intermediate layer with a portion of the surface layer to prevent attack on the peripheral edge during the subsequent treatme...