A ghost canceller which operates at IF and utilizes a storage mode heterojunction acoustic charge transport device (SM-HACT). The signal delay provided by the SM-HACT is increased by the operation of barrier electrodes which delay the movement of charge packets across the device, thereby eliminating the need for additional digital equalization. The tap weights of the SM-HACT are determined by the operation of a fixed correlator which responds to ghosts in a predetermined training waveform.

The accel electrode in a Kaufman-type of electron bombardment ion thrustor is created by interengaging panels of insulative material. These panels are angularly related to each other to define the openings of the accel electrode. Conductive blades are installed in each opening for electrostatic deflection of the beamlet issuing therethrough.

A thin film transistor including a thin semiconductor film which has a central portion as a channel region, with the side portions of the semiconductor film except for the channel region being a source and a drain regions which includes n-type impurities such as phosphorus ions of high concentration (3.times.10.sup.15 atoms/cm.sup.2), and a low concentration region provided between the channel region and each of the source and drain regions including p-type impurities such as boron ions of a low...

A thin film transistor and a method which forms a channel region (c), a lightly doped drain region (LDD) region and, optionally, an offset region (o), in a portion of a semiconductor layer which is adjacent a sidewall of the gate electrode without the use of photo masks, thereby increasing the permissible degree of miniaturization and improving production yield.

E and D mode HEMTs are integrated in a laminated layer of pairs of GaAs/AlGaAs layers formed on the same GaAs-on-Si substrate. The gate electrodes of E and D mode HEMTs are formed on different GaAs layers. The GaAs layer on Si contains crystal defects. It is hypothesized that the defects extend upward in the laminated layer of pairs of GaAs/AlGaAs layers formed on the GaAs layer with such crystal defects. Etch pits are generated as the AlGaAs layer is etched by ammonium etchant. Generation of et...

A semiconductor device has a plurality of transistor pairs. Each transistor pair includes a p-channel current path having a pair of p-type current terminal regions arranged by sandwiching a high resistivity of a first channel region, an n-channel current path having a pair of n-type current terminal regions arranged by sandwiching a high resistivity of a second channel region. The first channel region and the second channel region exert each electric field on each other by their intrinsic charge...

A flash memory device that can be erased and programmed electrically, the flash memory device includes an array of transistor memory cell units each has N-doped source and drain regions formed in the device substrate. An N-doped buried channel is formed in the device substrate located between the source and drain regions. A P-doped floating gate is further formed substantially above the buried channel, and a control gate is formed on top of the floating gate. The different doping pattern in the ...

A depletion type MISFET is formed on a surface of the semiconductor substrate, MISFET including a source region, a drain region, a channel region between the source and drain regions, a gate insulating film on the channel region, and a gate electrode on the gate insulating film. An impurity diffusion region is formed in a surface layer of the semiconductor substrate. An interconnect electrically connects the gate electrode and impurity diffusion region. A p-n junction is reversed biased when a v...

A thin film transistor includes an active layer having an offset region formed between a channel region and a drain region, a first insulating film formed on an upper surface of the active layer, a gate electrode formed at a position opposing to the channel region with the first insulating film interposed, and a second insulating film formed at a position opposing to the offset region with the first insulating film interposed and including impurities for forming charges. The charges formed in th...

A semiconductor integrated circuit comprising: a first power line which supplies a first voltage potential; a second power line which supplies a second voltage potential that is lower than the first voltage potential; a voltage regulator circuit connected electrically to the first and second power lines; a third power line which supplies a constant voltage generated by a voltage regulator circuit, with reference to the first voltage potential; and an operating circuit connected electrically to t...