An input buffer circuit achieving rail-to-rail operation maintains a uniform common mode output voltage even though an input signal having any voltage level is inputted. The input buffer circuit has a differential amplifier structure receiving two differential input signals. A first input part has a first inverter circuit into which a first differential input signal is inputted, and a second input part has a second inverter circuit into which the second differential input signal is inputted. The...

An output stage interface circuit for interfacing with a data bus, comprising first and second rails for receiving respectively a high voltage and a low voltage from a power supply; a data output terminal; a first main switch element coupled between said terminal and the first rail and comprising a first main MOS device having a gate and an independently configurable back gate, and responsive to a first data control signal applied to the gate pulling the voltage on the data output terminal towar...

The present invention provides a driving circuit. It includes a plurality of current mirrors to generate a first charge current and a second charge current in response to a reference current. A switch circuit generates a driving signal in response to an input signal. A driving switch is coupled between the first charge current and the switch circuit. Once the driving switch is turned on and the level of the input signal is in high level, the switch circuit generates the driving signal, the level...

A semiconductor device for improving an operation speed of a data input buffer includes: a plurality of data input buffers each for detecting a logic level of an input data by comparing the input data with a reference voltage to output the detected signal as an internal data signal; and a base voltage driving unit for driving a base power supply terminal of each data input buffer with one of a ground voltage and a negative boosted voltage according to an operation mode.

A power-voltage driver circuit includes a first MOS transistor configured to turn a second MOS transistor off when a high-voltage generator provides a high voltage output. Related methods are also disclosed.

Techniques are provided for trimming drive current in output drivers to compensate for process variations, model inaccuracies, and/or an off-target process. The actual output drive current is measured on the integrated circuit (IC) at wafer sort or during a final test. Based on the measured output drive current, the total transistor width that is required in the output driver to meet an I/O standard is calculated. A control block controls trimming transistors that are coupled in parallel with ma...

Circuits, methods and systems are provided to reduce skew between a first digital signal that is transmitted by a first driver circuit over a first signal line, and a second digital signal that is transmitted by a second driver circuit over a second signal line. Skew may be reduced by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the second digital signal transitioning to opposite logical values, and otherwise refraining from ...

A driver circuit for outputting an output signal corresponding to an input signal given to the driver circuit, includes a voltage generating unit for outputting a basic output voltage corresponding to the input signal, a first buffer circuit for outputting an output voltage corresponding to the basic output voltage outputted by the voltage generating unit, a second buffer circuit, of which power consumption is larger than the first buffer circuit, for generating and outputting a voltage correspo...

The present invention relates to an output driver circuit which exhibits a reduced variation in the slew rate of an output signal thereof, irrespective of a variation in temperature occurring during a process carried out by a semiconductor memory device, to which the output driver circuit is applied, or a variation in temperature caused by the operation characteristics of the semiconductor memory device, while exhibiting excellent operation characteristics even in a high-speed operation mode the...

A differential bus network, in general, or a controller area network (CAN) driver, in particular, controls and minimizes the variation on the common-mode signal of the CAN bus. This CAN driver also provides improved symmetry between its differential output signals, CANH and CANL, and provides protection for its low voltage devices from voltage transients occurring on its output lines. The common-mode signal is sensed and buffered, then during the dominant to recessive transition, the bus signals...