In differential amplifier circuitry formed on a semiconductor substrate, first and second transistors constitute a differential pair of the differential amplifier circuitry. First and second pads are connected with emitters of the first and second transistors, respectively. The first and second pads are connected with first and second external ground terminals via first and second rewiring layers to be grounded, respectively. The first and second rewiring layers are preferably connected with eac...

A method and apparatus for an automatic gain control circuit (AGC) that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the...

Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even ...

A monolithically integrated microwave frequency high power amplifier device comprises a plurality of transistors connected in a load modulation configuration wherein the number of the transistors that is operational depends on the drive level. The transistors have each a finger type layout, where fingers from different ones of the transistors are interleaved. The sources of the plurality of transistors are typically interconnected, whereas the gates of the transistors have separate connections f...

A multiple op amp IC with a single low noise op amp configuration comprises at least two op amp circuits fabricated on a common substrate. The IC can be configured such that the multiple op amps are connected in parallel to form a single op amp having output drive and input-referred noise characteristics which are superior to those of the constituent op amps. The IC can be fabricated with either first or second metallization patterns, with the first pattern providing multiple op amps with separa...

Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies.

A system for reducing the calibration time of a Power Amplifier (PA) (202) is provided. The system includes a memory module (304) that is integrated in the PA. The memory module is configured to store one or more calibration parameters of the PA.

A method and apparatus for an automatic gain control (AGC) loop that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FR...

In one embodiment, an output transistor and a bias compensation device are placed in proximity to each other on the same package substrate. The bias compensation device is electrically isolated but thermally coupled to the output transistor, and is configured to provide a output signal for adjusting bias to the output transistor.

The transistor circuit 1 includes a plurality of transistor cells 10 each having a transistor 11, a base ballast resistor 12, a capacitor 13, and an inductor 14. The transistors 11 have the respective collectors commonly connected to a collector terminal 1c of the transistor circuit 1 and the respective emitters commonly connected to an emitter terminal 1e thereof. Each base ballast resistor 12 is connected to bases of the transistor 11 at one end and to a base terminal 1b of the transistor circ...