The system of the present invention provides for the flow control of commands to devices connected through the system's memory management unit and is particularly useful in a multi-tasking computer system in which multiple processes access the same device. In the method and apparatus of the present invention, devices that are connected to the system through the MMU are controlled using the page fault mechanism of the MMU and the page fault handler in each segment. Addresses are allocated in the ...

The abbreviated jump field of the present invention enables each instruction word within the data processing apparatus to cause an instruction sequence branch to one of a limited number of destinations. Each instruction word of the data processing apparatus includes a limited number of bits which are decoded to specify one of a small set of instruction destinations. One of the possible destinations is the normal default destination of the next instruction word. In addition a relatively large num...

A method for selecting the sizes and the ordering of the extents used to construct a file, a segment, or a virtual space of a computer system (file). The general method is defined to be any function, applied to this purpose, that, in general, attaches larger extents to the larger file addresses, and for which the selection of extent sizes is determined only by the address an extent is to reside at in the file, plus any tuning parameters. The method results in files which are mostly contiguous, a...

A processor is disclosed having improved circuitry for (1) generating m+n-bit address words from n-bit data words and (2) converting m+n-bit address words back into data words having an n-bit format. The processor includes a first arithmetic unit (AMU) that is n bits wide and which receives n-bit words from a data bus. The processor further includes a second AMU that is m bits wide and which is connected to receive the m least significant bits of an n-bit word stored in the first AMU. An m+n-bit...

A microprogrammed processor having a bit-addressable scratch pad memory with variable length operands and a method of operation which increase processor operating speed, permit use of simpler interpretive firmware, and require a reduced amount of firmware memory than prior microprogrammed processors. Microinstructions each including a six bit op code field and first and second five bit address fields are stored in a high speed firmware memory. The two address fields are transferred to address in...

An improved data transfer apparatus and method is fabricated by multiplexing at least a portion of the address of the peripherals on the data bus. Data transfer is simplified by adopting identical control timing for the read and write cycles, setting up address and data information early within a cycle and synchronizing the output of such information on the output busses coupled to the peripherals. Data transfer control signals may be encoded to simplify read and write input/output and memory op...

A hierarchially arranged memory system is described for a data processing system having virtual addressing. A three-level working memory is provided, along with an auxiliary memory, in a data processing system containing a secondary buffer between the main memory and a rapid buffer memory. Whereas the main memory contains all actual storage areas, i.e. the memory pages of the inactive processes which were required for the processing period just passed, the actual storage area for the successor p...

A single chip large scale integration processor possesses its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function...

A computer system having a "program call instruction" which enables the use of a common program in a plurality of main program systems. The program call instruction has a pair of address parts (A) and (B), the first address part (A) is transferred to the program counter which indicates the current excuted program address and the second address part is transferred to the second push down stack. Before excuting the program call instruction the content of the program counter is transferred to the f...

Units peripheral to a data processor and individually selectable by unique address signals to perform functions are arranged in sets providing functions of hard wired apparatus such as data modems, units in each set providing functions identical to corresponding units in other sets. The performance of the functions is controlled by a memory unit which designates which modem set is to be selected and by a common program routine which instructs the processor to apply, to an address bus, address co...