A code synchronizing apparatus for synchronizing a local pseudo-random binary-sequence code generator with signals of a pseudo-random binary-sequence carried on incoming signals from a remote source, includes a sampler for obtaining sequences of samples of an input signal and of local code signals from a signal generator, a correlator for correlating the sequences of samples with those of local code signals which are offset by different integral numbers of bit-periods from a sequence of local co...

A convolution arithmetic circuit has a multiplier/accumulator to multiply two digital data sequences and add up the products. The sequences are stored in memories which cycle at the same rates and with different scales. One memory containing the multiplicand data is periodically updated, while the other memory containing coefficient data has a storage capacity of about twice the previous memory.

A convolution arithmetic circuit has an accumulator to multiply two digital data sequences and add up the products. The sequences are stored in memories which cycle at the same rates and with different scales, the memory containing the multiplicand data being periodically updated.

A convolving element which processes sixteen 4-bit samples but may be expanded to convolve both a larger number of samples and a larger number of bits per sample. The expansion occurs through interconnections of identical convolving elements. A selective inversion element inverts particular ones of the convolved samples under the control of a previously loaded binary code. The selective inversion element additionally minimizes interconnections and therefore input/output terminals of the convolvi...

A means for reducing side lobe signals and noise signals generated in a correlator in N chip positions for correlating a received input signal with a reference signal. The coincidence and non-coincidence indicating signals of first and second halves of the chip positions of the correlator are added together separately and then subtracted one from the other, with the resulting difference signal then being rectified. Such rectified difference signal which contains the side lobe signals and the noi...

Disclosed are polyester multi-filamentary yarn useful as a reinforcement for tires and a dipped cord formed therefrom. The polyester multi-filamentary yarn comprises at least 90 mol % of polyethylene terephthalate and has an intrinsic viscosity of 0.70.about.1.2 and a tenacity of 5.5.about.8.5 g/d with an intermediate elongation difference (E1-E0) between intermediate elongations E0 and E1 amounting to 6% or greater. The polyester dipped cord is produced by subjecting at least two strands of pol...

An adaptive processing system for real-time signal processing of one or more input signals in parallel-pipeline fashion is provided. According to the invention, the adaptive processing system includes a random access processor having an array of processing elements each being individually configurable. A man-machine interface receives instructions defining how an input signal is to be processed by the random access processor. A configuration controller responsive to the interface is used to gene...

A programmable correlator correlates a sampled information signal with a programmable reference signal. The correlator utilizes a plurality of stages. Each stage includes an information register, a multiplier, and a reference register. The correlator in some embodiments permits storage in the reference registers of a series of samples of a signal related to the reference signal during the time that the sampled information signal is cascaded from one information register to the next.

A correlator which is capable of correlating two or more signals of unknown frequency and bandwidth receives inputs on each of two or more channels. For the case of a two-channel, or pairwise, correlator the two channels are designated a first channel and a second channel. For the pairwise correlator, a first adaptive linear predictive (ALP) filter filters the input signal from the first channel and a second ALP filter filters the input signal from the second channel, the two output signals of t...

The processing unit includes at least one complex multiplier having hour multiplying circuits for multiplying the real and imaginary components of two complex vectors and combining the products to produce a complex output vector. Representing the input complex vectors by (A+jB) and (C+jD) the output complex vector becomes (AC-BD)+j(BC+AD). The combining circuits can be switched so that one of the input complex vectors is conjugated and the output complex vector becomes (AC+BD)+j(BC-AD). Thus, th...