A memory cell uses a pair of cantilevers to store a bit of information. Changing the relative position of the cantilevers determines whether they are electrically conducting or not. The on and off state of this mechanical latch is switched by using, for example, electrostatic, electromagnetic or thermal forces applied sequentially on the two cantilevers to change their relative position. The amount of power required to change the state of the cell is reduced by supporting at least one of the can...

A circuit board comprises a base film that is a base layer, a first conductive circuit manufactured by hardening conductive paste material formed in a predetermined shape on the base film, a first insulating layer manufactured by hardening insulating paste material formed on the base film and the first conductive circuit, and a second conductive circuit manufactured by hardening conductive paste material in a predetermined shape on the first insulating layer, wherein an electronic part built-in ...

A nonvolatile memory device features a hybrid switch cell as a cross-point cell using a nonvolatile ferroelectric capacitor and a hybrid switch. The hybrid switch cell comprises a ferroelectric capacitor and a hybrid switch. The ferroelectric capacitor, located where a word line and a bit line are crossed, stores values of logic data. The hybrid switch is connected between the ferroelectric capacitor and the bit line and selectively switched depending on voltages applied to the word line. The no...

A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

A ferroelectric non-volatile memory device comprising a MOS cell transistor, two ferroelectric capacitors each of which has one terminal connected to the gate electrode of the cell transistor and has almost the same remanent polarization, and a selector transistor connected to the other terminal of one ferroelectric capacitor, wherein data is stored by polarizing the ferroelectric thin films of the capacitors in opposite directions with respect to the gate electrode of the cell transistor.

A one-transistor FeRAM memory cell array includes an array of ferroelectric transistors arranged in rows and columns, each transistor having a source, a drain, a channel, a gate oxide layer over the channel and a ferroelectric stack formed on the gate oxide layer; word lines connecting the gate ferroelectric stack top electrodes of transistors in a row of the array; a connection to the channel of all transistors in the array formed by a substrate well; a set of first bit lines connecting the sou...

A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.

Electronic systems Si/Ge substrates. The electronic systems can include data storage devices and/or logic devices having active regions extending into a crystalline Si/Ge material. An entirety of the portion of an active region within the crystalline Si/Ge material can be within a single crystal of the material. The assemblies can be utilized for detecting properties of objects, and in particular aspects can be incorporated into assemblies utilized for identifying persons. The assemblies can be ...

A row redundancy circuit comprises a fuse box group array, a redundant row predecoder and a redundant sub-row decoder. The fuse box group array which comprises a plurality of fuse box groups detects whether repaired row addresses are applied. Each fuse box group consists of at least two or more fuse boxes to detect row addresses. The redundant row predecoder performs a logic operation on an output signal from each fuse box group to selectively activate redundant main wordlines each of which corr...

A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The s...