A bipolar random access memory array including "end of write shut down circuit means" coupled to the write circuit means is disclosed. The "end of write shut down circuit means" is activated by and only functions as the written cell switches state. The "end of write circuit means" is coupled between the opposite bit line and preferably the write transistor of a write circuit of the write circuit means. The use of "the end of write circuit means" improves the overall operation of the memory and i...

The present invention provides an organic bistable device for use in non-volatile memories. The organic bistable device comprises a first and a second metal electrode sandwiching a first and a second organic layer with a metal-nanocluster layer positioned between the first and second organic layers. The device further comprises a first electron blocking layer positioned between the metal-nanocluster layer and one of the metal electrodes. This structure provides an organic bistable device with im...

A gain memory cell circuit includes a storage capacitor connected between a storage node and ground, a write word line, a read word line, a second capacitor capactively coupling the read word line to the storage node, a read transistor having its source/drain path coupled between the bit line and ground and having its gate coupled to the storage node, and a write transistor having its source/drain path coupled between the storage node and bit line and a control electrode connected to the write w...

High emitter-coupled logic switching speeds and low standby power are achieved with a dual-port RAM cell in which two NPN Schottky transistors in a non-saturable bistable flip-flop configuration are flanked by a second pair of transistors whose collectors are individually coupled to the flip-flop collectors. The two output digit lines of the RAM are individually connected to the emitters of the flanking transistors, and their bases are individually coupled to the two select lines. A read signal ...

Disclosed is a simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology. The simulated storage cell structure includes n elongated regions of P-type diffusion arranged in parallel to each other in an N-type trough of semiconductor material. The elongated P-type regions are alternately designed as collector and Injector strips.

A decoder for address inputs to a semiconductor memory or the like comprises a NOR gate having a number of parallel input transistors corresponding to the number of address bits to be decoded. The address bits and their complements are selectively connected to the gates of the input transistors and the sources of these transistors, rather than only to the gates as in prior decoders. The layout of this decoder more nearly matches the pitch of rows in a high density dynamic RAM.

A plurality of single transistor memory cells with electrically charged capacitors and two similar dummy memory cells are electrically coupled in symmetric relationship to a sense amplifier for each row of the disclosed memory circuit. An address signal selects a word line connected to the memory cell on one side of the amplifier and a dummy word line connected to the dummy memory cell on its other side and applies a word signal to the selected word lines, in order to read out electric charges o...

This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order.

A static Random-Access-Memory having a single bit line between each pair of adjacent columns of memory cells, implemented in a self-aligned, N-channel, silicon-gate system. Resistor element load devices are made in second-level polycrystalline silicon by an ion implant step. The second-level polycrystalline silicon is insulated from the first-level polycrystalline silicon by a multiple oxide insulation layer. An additional word line for each row of memory cells provides differentiation between a...

Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting o...