A low power, low area shift register permits control over delay by dividing the shift register cells into a plurality of segments that are serially connected. A first selector provides data from a shift register input selectively to an input of one of the segments. A second selector provides data from an input or output of a selected cell of one segment of shift register cells to a shift register output.

A processing apparatus uses dynamic scaling of voltage (DVS) and includes a controller. This is particularly applicable to software defined radio (SDR), but may also be for other reconfigurable electronic systems. The controller includes a plurality of processing resources at least some of which have controllable supply voltage and/or frequency. The controller schedules operations on the resources, at least some of which have a predetermined deadline by which the operation must be performed, det...

There are disclosed herein equipment and methods for screening and concentrating wastewater overflow from combined sewer systems. Exemplary equipment includes a separator employing a substantially cylindrical rotating screen. Influent is piped upwardly into the equipment and deflected outwardly toward the inner surface of the screen in a manner to achieve a desired flow rate and flow pattern of the influent onto the screen. Means are provided for controlling the flow rate and for suitably direct...

There are disclosed herein equipment and methods for screening and concentrating waste water overflow from combined sewer systems. Exemplary equipment includes a separator employing a substantially cylindrical rotating screen. Influent is piped upwardly into the equipment and deflected outwardly toward the inner surface of the screen in a manner to achieve a desired flow rate and flow pattern of the influent onto the screen. Means are provided for controlling the flow rate and for suitably direc...

There are disclosed herein equipment and methods for screening and concentrating waste water overflow from combined sewer systems. Exemplary equipment includes a separator employing a substantially cylindrical rotating screen. Influent is piped upwardly into the equipment and deflected outwardly toward the inner surface of the screen in a manner to achieve a desired flow rate and flow pattern of the influent onto the screen. Means are provided for controlling the flow rate and for suitably direc...

There is disclosed herein equipment and methods for screening and concentrating wastewater overflow from combined sewer systems and the like. Exemplary equipment includes a separator employing a substantially cylindrical rotating screen. Influent is piped upwardly into the equipment and deflected outwardly by plural distributors toward the inner surface of the screen in a manner to achieve a desired flow rate and flow pattern of the influent onto the screen. Means including the distributors are ...

A centrifugal hydroextractor for fibrous material processing, comprising a rotating basket and a dispensing member for the material to be processed, which is rotatably mounted coaxially with and internally of said basket. The dispensing member is provided with material guide paths from the center to the side walls of the basket; at least one disc valve, closing the basket at the top, is fast with said dispenser and has a central aperture for the material supply and a number of peripheral ports c...

A shift-register circuit. The PMOS transistor includes a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS tr...

A shift-register circuit. The input circuit receives the input pulse and outputs a high-voltage level input signal when the input pulse is at high voltage level. The level shifting circuit includes a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD, a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD, a first inverse logic g...

A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node .alpha. is raised. When the potential of the node .alpha. reaches (VDD-VthN), the node .alpha. becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential o...