A circuit arrangement as part of a shift register is proposed for controlling switch elements arranged in the form of a chain or a matrix, including four clock signals that are phase shifted by 90.degree. with respect to one another for the control, with at least one transistor switching through a signal that is independent of the shift clock signals to the output to control the switch elements depending on the information to be shifted.

A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node .alpha. is raised. When the potential of the node .alpha. reaches (VDD-VthN), the node .alpha. becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential o...

A bi-directional shift-register circuit for outputting data in different turns according to a switching signal. Each shift-register unit includes a first input terminal, a second input terminal, an output terminal and a clock input terminal for receiving the clock signal. The first switching circuit is coupled to the output terminal of the pre-stage shift-register unit, the output terminal of the next-stage shift-register unit and the switching signal, and outputs the signal of the output termin...

A shift register having several cascaded stages, each stage containing an output at a first node connected to a next stage, a first input connected to an output of a preceding stage, a second input connected to an output of the next stage and a first terminal connected to a first clock signal and a second terminal connected to a second clock signal, the stage containing a first semiconductor device switching the output of the stage between high and low values of the first clock signal, the first...

The subject of the present invention is a shift register for an LCD, the stages of which use the Boostrap [sic] effect and can contain just three M.I.S. transistors, as well as enhancements to this circuit with four or seven MIS transistors. The advantages are the low number of components used, the increase in the lifetime of the shift register and the possibility of working with control signals having an amplitude of 5 or 10 v below that of the output signals.

A shift-register circuit. The PMOS transistor includes a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS tr...

A shift-register circuit. The input circuit receives the input pulse and outputs a high-voltage level input signal when the input pulse is at high voltage level. The level shifting circuit includes a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD, a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD, a first inverse logic g...

A shift register which is stably operable even under low power voltage and including a first transfer gate NTM1 connected to a data input terminal DIN1, second and third transfer gates NTM2 and NTM3 connected in series to a ground line, a pair of inverters IVM1 and IVM2 connected in the opposite orientation between the output terminals of the first and third gates, and fourth and fifth transfer gates NTS1 and NTS2 connected in parallel with respect to the outputs of the pair of inverters IVM1 an...

An improved dynamic shift register circuit is disclosed. A circuit design is provided to minimize overlapping between two adjacent output pulses in the dynamic shift register circuit. In an application of analog sample-and-hold circuit, the circuit design effectively improves a distortion of sampled data caused by significant overlapping of two adjacent output pulses as control signals.

The present invention concerns a process to produce a high surface area niobium oxynitride, tantalum oxynitride, vanadium oxynitride, zirconium oxynitride, titanium oxynitride or molybdenum oxynitride coated substrate for use as an electrical energy storage component in a capacitor or a battery configuration. The process relates to: (a) coating one or both flat etched surfaces of a solid substrate, in the form of a thin sheet, with a solution or a slurry of a metal halide in a liquid volatile ca...