A bi-directional shift-register circuit for outputting data in different sequence. A first shift-register unit includes a first-stage control terminal and a first-stage output terminal outputs a first output signal. A second shift-register unit includes a second-stage input terminal coupled to the first-stage output terminal and a third-stage output terminal, a second-stage control terminal and a second-stage output terminal outputs a second output signal. The second-stage control terminal is se...

An interleaved shift register 20 includes a plurality of data storage elements 22a-22d having a common data input signal. Each of the plurality of data storage elements 22a-22d has an enable control input that is connected to one of a plurality of clock signals, each of the plurality of clock signals being incrementally out of phase with one another. Interleaved shift register 20 provides multiple data bits of the data signal to be stored within a single clock period of one of the plurality of c...

A new class of shift registers that shift the contents of a 2.sup.n bit length register up to 2.sup.n -1 positions in n cycles. Shift registers according to the present invention can be constructed to shift left, shift right, or to shift either left or right. A general implementation of this class of shift registers comprises the following hardware: 2.sup.n D flip-flops or D latches for the data register positions of the shift register; logic for each of the 2.sup.n positions to determine the in...

An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of "pre-load" flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable s...

An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback...

In this invention compare circuitry is integrated into a serial shift register which can detect a bit pattern of any length with only the delay of three circuits being added to the shift of the last bit in the bit pattern. The circuitry is connected to operate either is a shift register or as a comparator for an N element bit pattern. Between adjacent registers in the shift register is a MUX used to select compare or shift register operation. An exclusive NOR circuit performs the compare between...

A simplified bi-directional shift register and a single-latch circuit for implementing the bi-directional shift register thereof which obviates the use of a conventional dual-latch (i.e., master/slave) configuration in the bi-directional shift register design is described. The single-latch circuit includes an input circuit portion and a latching circuit portion. The input circuit portion receives input signals including the output data from previous and next single-latch circuits in the shift re...

A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage a selected number of stages ahead in the chain and to the disable input of a stage a selected number of stages behind in the chain.

A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by programming selected memory cells. The programmable shift register includes a plurality of flip-flops, a programmable interconnect circuit, a next-state control circuit and a mode control circuit. The output terminal of each flip-flop drives a different bus line in the programmable interconnect circuit. Each bus...

A shift register is clocked by propagating two clock networks in opposite directions: one from input towards the output, the other from the output towards the input. The parasitic delays at the end of these networks are picked to be approximately equal. An extra latch is added to the shift register where the two clock networks meet to prevent a race condition. Both clock networks consist of non-overlapping clocks. Non-overlapping clock generator circuits are used to restore the non-overlap of th...