An image data monitor apparatus has a CCD for reading image data of a document, an input buffer for receiving the pixel data from the CCD, an image processor for processing the data received from the CCD for printing out an image or the like, a circuit including a counter for extracting the designated pixel data, a keyboard for setting a desired mode, LEDs for displaying the extracted pixel data and other data, and a CPU for controlling the operation of the overall system. Various data such as m...

An image processing apparatus includes an image memory for storing digital image data obtained by A/D-converting a video signal, an arithmetic circuit for performing an arithmetic operation of the image data so as to emphasize an edge, a first plane memory for storing the edge image data, and a second plane memory for storing binary data of all "1"s or "0"s. The first and second plane memories are addressed in response to address data from an address generator. The readout edge image data and th...

Apparatus for processing images which have been sampled on a rectangular grid and which have been binary digitized with one bit per pixel, each pixel being considered in relation to at least some of the eight surrounding pixels in the rectangular grid. The apparatus includes a control unit (4), a random access memory (5) for storing the pixel bits, and a feedback loop connecting the image memory output to its input via at least one feedback assembly (6) comprising shift register unit (6A, 6B), a...

An image processing system for computing morphological characteristics of object regions in a binary image frame. The characteristics are generated at the frame rate. One embodiment utilizes an architecture including an interconnected delay component, bit packing component and LUT. The output values provided by the LUT are accumulated over one frame cycle to compute morphological characteristics.

A system of reconfigurable pipelines of generalized neighborhood function morphic image processors provides image transformations. An input image pixel stream is provided to one or more reconfigurable processing element groups comprising reconfigurable delay RAMs, reconfigurable neighborhood function RAMs, and reconfigurable window selection switching in order to achieve general neighborhood window function morphic image transformations. The described arrangement is amenable to VLSI packing impl...

An image processing system for extracting a plurality of local images each composed of m.times.n pixels, successively from a two-dimensional original image, to process the extracted local images and to convert the original imae into a second image composed of modified pixel data corresponding to the local images is disclosed which system includes a plurality of local image extracting circuits for temporarily storing time-sequentially applied pixel data in each local image extracting circuit whil...

A method for coding an image or other two-dimensional data array to provide a sequence of images having differing spatial frequency content is disclosed. The method generates the output images by taking weighted sums of the pixels in the input image. The weights are sets of two-dimensional irreducible scaling and wavelet coefficients.

A signal processing device for generating an output signal corresponding to a multi-dimensional input signal such as a two-dimensional image and a method of processing such a signal. The device includes an array of processing elements which are congruent and shaped so that they can be arranged on a processing element so that adjacent pairs of elements considered as a unit are geometrically similar to each processing element. Output signals of individual processing units are linearly ordered in s...

A programmable general purpose digital image processing circuit 30 incorporates pipeline image processing architecture including one or more pipeline processing chains 379 for making image processing computations, each chain comprising a serial connection of a convolution (CONVOL) unit 34, logic (LU) unit 35, morphological (MORPH) unit 36 and look-up table (LUT) unit 37, which enables the greatest number of processing operations to be performed within the shortest possible overhead time.

An image data processor comprises a memory for storing image data, an image data processing unit for processing the image data stored in the memory, and an address calculation unit operating in parallel with the image data processing unit for calculating the addresses of the image data and controlling input/output to and from the image data processing unit. The image data processor can execute processings of image data such as extraction, deletion, synthesization or the like of the image data at...