The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each other and connected to the same overlying bump. In a second embodiment, each BLM is split into more than two segments. In a third embodiment, each segment is electrically connected to more than one underlying via. In a fourth embodiment, each segment is electrically connected to more than one underlying...

A bump is formed on a semiconductor wafer which has a pad electrode thereon. The method includes the steps for coating a first organic film on a semiconductor water; drying the first organic film; applying an excimer laser to a portion of the first organic film substantially corresponding to the pad electrode to thereby form a first opening in the organic film; forming at least one metallic film on the first organic film and the opening; coating a second organic film on the metallic film; drying...

A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photo...

Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film, each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to com...

An integrated circuit chip 903, which has a plurality of pads 903b and non-reflowable contact members 1201 to be connected by reflow attachment to external parts. Each of these contact members 1201 has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface 1202 on each end and a layer of reflowable material on each end. Each member is solder-attached (1204) at one end to a chip contact pad 903b, while t...

Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpie...

In one embodiment, conductors of a semiconductor device are routed to a contact platform of the semiconductor device by using electroless plating and screen-printing techniques.

A circuit device includes at least one under bump metal formed on a surface of a substrate and a connection bump provided on the uppermost layer of the under bump metal. At least one laminated metallic film is formed on part of or all of wiring pattern formed on the surface of the substrate, so that the laminated metallic film formed consists of the same material and has the same thickness as the under bump metal.

A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a second UBM layer may be formed on the first photoresist pattern. A second photoresist pattern may be formed that exposes the first UBM layer and covers the second UBM layer. A solder bump may be formed in the opening. The second photo...

A semiconductor component includes a substrate having a plurality of compliant contact bumps formed over a surface thereof. A semiconductor chip has a plurality of contact regions formed over a surface thereof. The compliant contact bumps of the substrate are electrically connected with the contact regions of the semiconductor chip and wherein the semiconductor chip is mechanically attached to the substrate. As an example, this connection and attachment can be achieved by soldering the contact b...