A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, a...

A method for manufacturing a semiconductor device including providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area formed with a device element density lower than the device element density of the cell area. An insulating layer is deposited over the semiconductor substrate. The insulating layer is planarized through a chemical mechanical polishing (CMP) process including a first polishing step and a second polishing ste...

A self-aligned via structure and its method of manufacture comprising the steps of providing a semiconductor substrate, and then sequentially forming a conductive layer and a dielectric layer over the substrate. Next, a hollow cavity is etched out in the dielectric layer. Then, a photolithographic process is performed by coating a photoresist layer over the dielectric layer and the cavity, followed by creating a pattern of desired conductive lines so that portions of the photoresist layer overla...

Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the-hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor depo...

A common axis, multi-pole connector assembly provides improved connectivity with electronic devices having mating receptacles of differing form factors. In one aspect, the connector includes assembly includes a single pin, hollow plug body, one or more conductive lines extending within the plug body, and a sleeve configured for sliding reception over the plug body. The plug body is formed with one or more discrete conductive contacts with which the one or more conductive lines are electrically c...

Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. More...

An object of the present invention is to provide a method for manufacturing a display device with few steps and high yield. One feature of the invention is to form a first mask pattern having low wettability over a conductive layer, form a second mask pattern having high wettability over the conductive layer using the first mask pattern as a mask, and form a mask pattern for etching the conductive layer by removing the first mask pattern. Another feature is to form a pixel electrode by etching t...

A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corres...

A method enhances selectivity between a film of a light-sensitive material and a layer to be subjected to etching in the course of fabrication processes of an electronic semiconductor device starting from a semiconductor material wafer. The method includes radiating the wafer with an ion beam subsequently to depositing the layer to be etched and defining a circuit pattern on the film of light-sensitive material. An alternative method exposes the wafer to a non-reactive gas medium under plasma ra...

A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.