Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Thereafter at least one electrically conductive interconnect line is exposed to ionized air.

A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device ...

Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the-hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor depo...

A memory cell having a bit line contact is provided. The memory cell may be a 6F.sup.2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surfac...

A method of fabricating a through via connection useful in providing a vertical wafer-to-wafer interconnect structure is provided as well as the vertical interconnect structure that is formed by this method. The method of the present invention using only a metal stud for the vertical connection therefore no alpha radiation is generated by the metal stud. The method of the present invention includes an inserting step, a heating step, a thinning step and backside processing.

A method of forming a contact hole of a semiconductor device is disclosed. At the time of a hard mask formation process for forming a contact hole of a semiconductor device, first patterns are formed using a photoresist pattern employing an exposure process. Spacers having a predetermined thickness are formed on sidewalls of the first patterns using an amorphous carbon layer. Spaces between the first patterns including the spacers are gap filled to form second patterns. Accordingly, a contact ho...

In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.

A multi-layer semiconductor device including copper interconnects with improved interlayer adhesion and a method for forming the same, the method including providing a semiconductor substrate comprising a dielectric insulating layer comprising copper containing interconnects the dielectric insulating layer and copper containing interconnects comprising an exposed surface; forming a first capping layer on the exposed surface; providing a treatment on the first capping layer to increase interface ...

A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is formed over the selected substrate level and within the alignment recess, wherein the alignment recess is formed at a depth such that the first metal layer only partially fills the alignment recess. A second metal layer is formed over the first metal layer such that the alignment recess is completely fil...

The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein position...