A system and method for circuitry design verification testing which provides for maximized code re-use without unnecessary allocation of system resources. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class which collects convenience routines and thereby maximizes code re-use. The system transaction class contains pointers to device transaction classes which correspond to each of the functional models in the simulation subsyst...

A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf cell and the second leaf cell is also specified in Verilog syntax. This specifies a circuit. The functionality of the logic can be tested by running a logic simulation on the circuit without converting to Verilog syntax. The Verilog syn...

A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language includes a repository (10) storing a general set of self-checking tests applicable to the integrated circuits. A capability is provided for entering behavior data (21) of an integrated circuit model (20), and for entering configuration data (22) of the integrated circuit model. The generator automatically generates test benches (30) in the Hardware Description Langua...

A logic emulation system that verifies a target logic circuit and evaluates its performance efficiently divides the design data of a target logic circuit into a plurality of small-scale logic circuits and a connection circuit for interconnecting the small-scale logic circuits, thereby creating an equivalent circuit of the target logic circuit. The logic emulation system judges, when a logical design change to the target logic circuit prompts the comparison of the data of the equivalent circuit o...

A system and method is provided to accurately model bidirectional wire I/O using hardware description language (HDL). The preferred model and method uses an HDL model that provides two parallel paths between ports of the bidirectional wire I/O. During simulation, the ports are monitored for activity. When an event is detected on either port, the model checks both ports to see if they are different values. If the ports are different values, one of the two parallel paths is enabled and the other d...

A simulation executing unit includes a conversion unit and a simulation portion. The conversion unit includes a circuit dividing portion, a circuit converting portion and a converted logic circuit generating portion, and the circuit dividing portion divides a logic circuit into combinational partial circuits each interposed between registers or between a register and an input pin or the like. The circuit converting portion generates, on the basis of the divided combinational partial circuits, a ...

Disclosed is simulation of circuit behavior by running a central electronic core simulation in a high level simulator up to and including initial microload, creation of a post-IML (initial microcode load) state, and transferring the post-initial microcode state from the central electronic core simulation to the post-initial microcode load co-simulator.

A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signal...

A stabilizer unit having a pair of mounting rods adapted to extend fore and aft of a vehicle frame and to be pivoted at front ends thereof to locations near the outer ends of the rear axle of the vehicle. The rear ends of the mounting rods are adapted to be shiftably coupled by coil springs to respective bolts secured to and extending downwardly from respective frame members of the vehicle. A cross rod interconnects the rear ends of the mounting rods and acts as a sway bar. A pair of inflatable ...

The components of performance analysis considered within the scope of the invention are, in particular, the determination of the speed at which a circuit or a circuit component can generate output signals from input signals, and the noise immunity of the circuit. The process for evaluating the performance of a very high scale integrated circuit comprises: a first step (E1) in which, for each lead (L.sub.i) of said circuit, an equivalent coupling capacity value (C.sub.Ti) relative a fixed potenti...