The present invention allows more than two devices to be connected to a single ATA bus. The devices are each assigned a unique identifier, and a controller selects a device by sending a selection command that includes a selection identifier across data lines of the ATA bus to the devices. The devices each receive the selection command and compare the selection identifier to the assigned identifier. The device which matches the selection identifier to its assigned identifier is selected, and the ...

A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at least one reset signal generator. While a hot reset packet cannot be executed by the high-speed PCI device, the host controller chipset can respectively transmit a trigger signal and a PCI reset signal to each corresponding reset signal generator through a trigger signal line and a PCI reset signal line,...

Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored in the memory core during the write operation. A first bit of the write data is provided to the memory device during an even phase of a clock signal. A second bit of the write data is...

The present invention provides systems, methods, and bus controllers (12) for monitoring an event of interest via a network bus (14) and creating an asynchronous event trigger on the network bus indicating that the event occurred. Importantly, the systems, methods, and bus controllers (12) of the present invention use either one or several network devices (16, 18) that are connected to the network bus (14) and monitor the occurrence of an event of interest. These network devices (16, 18) are con...

A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data tra...

The invention concerns an arbitration scheme for permitting access to the bus of a computer. The arbitration scheme has the ability to control and reduce the delay experienced by any device by monitoring the queue length of the device and using information concerning the device, such as device rate, phase, data transfer size and queue length. Specifically, the arbiter prevents periodic accessing devices, such as audio and video samplers, from being delayed or interrupted for long periods of time...

Central processing units have two or more groups of in each case one processor, one memory and one coupler, the processor and memory are connected to exactly one coupler and the couplers are connected to one another. A memory area distributed uniformly over the address space is allocated disjointedly to each group by address interleaving and each coupler itself meets an access to the memory area allocated to its group and meets other accesses via the connection to the coupler concerned. The cent...

A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it has a snoop buffer available. However, rather than unconditionally processing the operation, the snooper waits to determine if another participant retried the operation due to unavailability of a snoop buffer. If some snooping participant retrys an operation, all snoopers that speculatively accepted an...

A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data tra...

The IEEE 1394 bus communication protocol has three layers: physical layer, link layer, and transaction layer. Typically, the transaction layer is realized by firmware whereas the other layers are implemented using chip sets. The link layer IC usually contains a FIFO having a capacity of e.g. 32k or 64k bits. Therefore, the link layer chip is the most costly part of a complete IEEE 1394 interface. Due to these cost reasons most ICs on the market are not bi-directional although the IEEE 1394 bus s...