A data processing structure comprising a plurality of processors ad a data bus for a data communication with a serial data structure. The plurality of processors can be respectively coupled in parallel to the data bus, and a data communication via the data bus with one of the processors, preferably a programming of the processor, is authorized for the same, but is blocked for all of the other processors.

Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.

A bus bridge which intercepts synchronization events and selectively flushes data in buffers within the bridge is disclosed. The bridge insures data consistency by actively intercepting synchronization events, including, interrupts, processor accesses of a control status registers, and I/O master accesses of shared memory space. Interrupt signals may be routed through the bridge, which includes a bridge control unit comprised of state machine logic for managing data transfers through the bridge....

A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus pas...

A multi CPU system is capable of performing exclusive control of a plurality of CPUs accessing to the same resource by a hardware without depending on an OS. The plurality of CPUs are connected with the same system bus. A plurality of circuits one-to-one correspond to each of the plurality of CPUs and comprise respective semaphore acquisition registers. Each of the CPUs in accessing to the resource is controlled, based on the value written in the semaphore acquisition register of the correspondi...

An almost full flag is asserted when all but one of the rows of a CAM array contain valid data, as indicated by corresponding valid bits. In one embodiment, the almost full flag is generating using match logic and multiple match logic, where the match logic asserts a first signal when at least one of the CAM rows contains invalid data, and the multiple match logic asserts a second signal when more than one CAM row contains invalid data. The almost full flag is asserted when the first asserting i...

An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established w...

A hydrometallurgical process for recovering copper from copper bearing ores or fractions, by a process of first wetting and sulfatizing the ore with controlled amounts of H.sub.2 SO.sub.4 and water, followed by acid curing and repulping to sulfatize a substantial portion of the copper in the ore. Also, the fine and coarse fractions can be classified, followed by pile leaching the coarse fraction, preferably reusing the cycled H.sub.2 SO.sub.4 solution obtained during the copper recovery process....

Described herein are techniques for global synchronization that under various scenarios eliminate or defer the acquisition of global locks. In many cases, the need to acquire global locks is eliminated, thereby saving the overhead attendant to processing global locks.

A system, including a specially-designed optical element, facilitates extremely precise and accurate registration of a light beam on a photoreceptor. The optical element includes a redirecting cylinder lens, having a longitudinal axis oriented obliquely relative to the scan path of the light beam to redirect the light beam. The redirected light beam interacts with an aperture in the photoreceptor to provide an accurate measuring device for the exact position of the aperture with each scan.